Last Edit July 22, 2001
There are no coverage rules for an at-speed analysis. It can be done
using a timing verifier or a simulator. The output format is vendor-specific
and in this case matches all other simulations performed for the circuit.
The at-speed simulation is to be run at the specified maximum operating
frequency of the circuit. The actual maximum frequency of this circuit
is left as a class exercise.
Two simulations are shown - Figure 8-4 shows the maximum worst-case sampled
simulation and Figure 8-5 shows the maximum worst-case print on change.
Sampling depends on the maximum frequency. The print on change file has
an entry for each time that a monitored signal changes state. (This version
of the circuit had 3-state outputs.)
Figure 8-4a At-Speed Sampled Simulation -
32-Bit Register (partial)
Figure 8-4b At-Speed Sampled Simulation -
32-Bit Register - Full listing
Figure 8-5a At-Speed Print-On Change Simulation
- 32-Bit Register (partial)
Figure 8-5b At-Speed Print-On-Change Simulation
- 32-Bit Register - Full listing
Note that there are no switching restrictions for outputs in a vector
for this simulation, which considerably reduces the size of the sampled
vector output file in comparison to that for the functional simulation.
The at-speed simulation is never run on a tester. The reset is handled
Create a complete at-speed vector set for the schematics shown in the
Appendix of Chapter 3 (no 3-state outputs).