Last Edit July 22, 2001
Power dissipation is a measure of the amount of heat that must be handled
by the array, its package, and the board on which they are mounted and
cooled by whatever means is used. Handling this heat, called thermal management,
is a fundamental design requirement. Estimating the heat to be dissipated
requires a worst-case maximum power dissipation computation.
The computation of the worst-case maximum power dissipation for a circuit
has two major components, DC (quiescent) power and AC (dynamic) power
dissipation. Each in turn is composed of several elements. While DC power
dissipation can be reasonably bounded by worst-case equations based on
P = I*V, AC power dissipation without hardware emulation-assist and complex
software is at best a rough guess.
Cell Types Define the Power Computation
Array and cell types can be broken down into four basic categories: CMOS,
bipolar, BiCMOS and super-speed bipolar (see Table 7-1):
- CMOS arrays have a significantly higher AC power dissipation figure
than DC power dissipation for most cells.
- Bipolar arrays have the DC power dissipation as the principal source
- BiCMOS arrays have a combination of these two approaches, following
bipolar computational procedures for I/O macros and CMOS computational
procedures for core macros.
- BiCMOS arrays (in proposal stages) would use bipolar methods for
any bipolar cells, interface and internal, and CMOS computations for
their CMOS cell based macros.
- High-speed bipolar (over 600MHz) requires the use of both approaches,
with neither DC or AC power being considered as insignificant factors.
In this case, AC power may be no more than 20% of the DC power (using
the Q20000 Series guideline).
Table 7-1 Cell Type Vs. Power Component
|Macro On Cell Type:
|| Principal Power Dissipation:
||both AC and DC
DC Power in a Bipolar Array
DC power dissipation computation for a bipolar array is composed of interface
macro DC power, internal macro DC power, overhead current DC power and
ECL static output power dissipation. DC power is a function of the current
dissipated, adjusted for state dependencies, junction temperature, voltage
levels, ECL termination values, and any conditional geo-metry power down
of IOEF. Typical DC power can be computed to a given level of detail from
the netlist of the circuit using:
P = I * V (one macro)
where I is the adjusted typical macro current from all current sources
(IOEF and internal current) and V is the power supply. A worst-case multiplier
can be used to convert typical DC power into worst-case power for a specific
set of conditions. Some components of DC power are shown in Table 7-2.
Table 7-2 DC Power Computation - Bipolar
|Computing DC Power
- Interface macro DC power
- Internal macro DC power
- Overhead current DC power
- ECL static DC power
- Reduction for state dependencies
- Reduction for power-down of IOEF
- Reduction for junction temperature
- Reduction for voltage levels
The array vendor may specify a typical macro current (summing internal
and IOEF values) and overhead current, or a typical macro PDC term, where
a power supply has been assumed and conversion factors exist to adjust
for differences. In this case, additional information as to ECL I/O bias
power usage will be supplied, as well as some means of handling ECL
DC power due to termination current. Regardless of the variations in
"specsmenship", the methods are algebraically the same, as they must be.
DC Power in a BiCMOS Array
The DC power component will be the significant factor in computing power
for the interface macros in a BiCMOS array. The power computation is the
same as was applied to the bipolar array, except that the computation
is made for the interface macros and not all macros in the circuit. Both
the power due to the current sources in the interface macros and the power
due to overhead current must be computed.
Overhead current (ICC and IEE) is that current dissipated by the voltage
threshold generators and bias circuitry. It will be dissipated even if
no macros are placed on any of the cells, i.e., it exists as soon as the
chip is powered on.
For some arrays, overhead current and therefore overhead power may be
specified as variable. It may depend on whether a specific type of I/O
macro was used anywhere on the circuit, or on the number of such macros
and their placement.
Placement-dependent computations cannot occur until after place and route.
Pre-placement computations must assume the worst possible conditions.
Overhead power is the overhead current times the power supply, computed
as for the macro power dissipation.
DC Power in a CMOS Array
DC power in a CMOS array is due to a static DC current (transistors are
ON) and a leakage DC current (transistors are OFF). There may also be
an overlap current, a result of both paired transistors being ON as they
The total value for leakage current will be low and needs to be measured
when the circuit can be configured with all devices off. Static DC current
should be approximately zero, or low enough not to consider. Power dissipation
due to overlap current is no more than 10% of the total power dissipation.
These figures are guidelines only. The designer should review the design
manual for the specific array to be used to determine the power characteristics
for that array.
TTL Outputs - CMOS Arrays
Power dissipation due to TTL outputs on a CMOS array needs to be included
in the total power computation. It is a function of the duty cycle of
the outputs and the sink current.
P = n * Isink * VOL
where n is the number of TTL loads, V is the output low voltage and I
is the sink current for the macro.
The specification may show a Pdc value instead of current for the individual
ECL Static Output Power - All Arrays
ECL output macros on bipolar or BiCMOS arrays dissipate a static power
based on the termination resistor value (off-chip termination). The com-mon
estimate for this current is:
P = I * V (per output)
where I is the termination current value (14 mA for a 50 ohm termination)
and V = 1.3V, the voltage swing for -5.2V termination.