External Set-Up and Hold Times
Last Edit July 22, 2001
Case Study: Preventing Hold Violations Due To Clock Skew
Hold Time Considerations
Assume a typical 32-Bit shift register being driven by two clocks. No
extraordinary design considerations are needed to maintain hold time when
the Q output and D input are on flip/flops that are driven by the same
clock net. (See Figure 6-4.) The AMCC Q5000 Bipolar macro library
is used in the example.
Figure 6-4 32-Bit Register: Single Clock Path
If the clock nets are different (Figure 6-5), the two clock paths
need to be analyzed to determine if the required hold time has been satisfied.
Differences in tracking, fan-out and metal lengths between the paths can
be significant and cause enough delay in the second path (PATH 2) to create
a hold time
Figure 6-5 32-Bit Register: Two Clock Paths, Balanced Tree
CLK through D1 and through clock->Q on FF15 is the data path for the
hold time computation for FF16. CLK through D2 and coming into the C input
of FF16 is the corresponding clock path. The macro hold time, shown as
Th for FF16, cannot be violated.