Timing Analysis for Arrays
Last Edit July 22, 2001
WorstCase Delay Multiplication Factors
Once the sum of all the typical intrinsic and extrinsic propagation delays
in a circuit or path segment is computed and adjusted for the output capacitive
load, then the result must be multiplied to obtain the worstcase delay
as follows:
T_{pdworstcase} = T_{pdtypical}
* adjustment
To perform worstcase analysis, the worstcase multipliers or adjustment
factors for the appropriate operating range must be used. Example bipolar
array multipliers are shown below. Refer to the appropriate design manual
for worstcase multipliers for a particular array series.
Many vendors specify a typical propagation delay, with or without assumed
loading. Delays due to fanout loads are also given for specific conditions.
When the power supply or temperature varies from the typical specification,
some derating must be applied to the typical delays. In addition, some
allowances for process variations should be made.
Some vendors specify the derating required for each of these items as
a separate number or curve while others provide a combined worstcase
multiplier, designed to assume that everything is in the worst possible
state.
There may different derating or worstcase multipliers for macros and
for the interconnect nets, and there may be different multipliers for
different macros.
For a given array, the designer needs to determine whether the worstcase
delay multipliers apply to setup, hold, recovery time or pulse width.
Array Series (Historical) Timing Adjustment Factors  Different Arrays
Examples
The Raytheon design manual uses charts and shows a variation for temperature
derating that spreads from 0.88 for 25C, to 1.15 for 150^{o}C
(1.10 for 130^{o}C). The chart for the voltage derating factor
varies from 0.98 at 5.72V (ECL 10K), to 1.05 at 4.68V (ECL 10K). The
same range applies ECL 100K; 0.98 at 4.95V, to 1.05 at 4.05V. The chart
for the process derating varies from 0.73 to 1.2. At a junction temperature
of Tj = 150^{o}C, these combine to form a worstcase derating
of 1.449 max and 0.63 min.
AMCC specifies a worstcase military maximum derating factor of 1.45
for its bipolar arrays and specifies a process variation of 1.19  1.45
(20% variation) in combination with the temperature and voltage variations.
The AMCC multipliers also account for temperature, voltage and process.
The minimum operating conditions use a worstcase range of 0.700.89.
They apply to both the intrinsic macro delays (t_{in} = Tpd)
and to the extrinsic loading delays (t_{ex}), both loading delays
on internal nets and loading delays on output macros due to capacitive
load.
For interconnect delays, Raytheon provides tables to allow an estimate
of fanout delays based on fanout load. They appear to be appear linear.
(See Table 55.) Additional tables provide derating factors to allow adjustment
for metal interconnect and metal temperature.
Table 55 Raytheon Adjustment Factors Factor/Variation (Historical)
Temperature 

0.88/25^{o}C 
1.05/130^{o}C 
1.15/150^{o}C 
Voltage 
ECL10K 
0.98/5.2V 

1.05/4.68V 

ECL100K 
0.98/4.95V 

1.05/4.05 
Process 

0.73 

1.2 
TOTAL 

0.63 MIN 

1.449 MAX 
AMCC uses a nonlinear equation to compute net loading and uses the macro
worstcase multipliers on the interconnect delays.
For older arrays, AMCC also specified a linear relationship based only
on fanout loading (0.5ns/load for rising edge; 1.0ns/load for falling
edge), also combined with the macro worstcase multipliers.
For the new BiCMOS series, the different technologies make different
multipliers necessary. There is one for the bipolar interface macros and
their extrinsic delays and one for the internal CMOS core macros and their
extrinsic delays. The internal core macro worstcase multipliers apply
to the setup, hold, recovery time and pulse width values. An array series
may have different multipliers for different arrays within the series.
Always verify the multipliers required, if any,
and verify when they are used.
Always go back to the latest information from the array
vendor.

