Timing Analysis for Arrays
Last Edit July 22, 2001
Example Equations for Extrinsic Loading Internal Nets
Loading delays may be computed for FrontAnnotation analysis by the general
equation:
 where:
 k = the kfactor for the series and the macro option
k_{fo} is for fanout load;
k_{net} is for metal load
k_{wo} is for wireOR load
L_{fo} = the sum of the electrical fanout loads in a net.
(Pins with a fanin of 2 count as 2 electrical loads.)
L_{net} = the estimated metal delay from Front Annotation tables
or equations;
L_{wo} = the electrical load due to wireOR
The kFactors are the conversion factors for changing load units into
time units. These kFactors are expressed in ns/LU. The load units are
computed for electrical fanout, net metalization and electrical wireOR
loads. The kFactors may be assumed to be identical for FrontAnnotation
estimation. If the array does not allow wireOR structures, the equation
reduces to:
t_{ex} = k * [ L_{fo} + L_{net} ] reduced
equation

L_{net}  FrontAnnotation
L_{net} is the statistical wire load taken from the FrontAnnotation
Statistical Wire Load table supplied by the vendor or from an equation
that is supplied by the vendor, using the number of physical pins in the
net minus 1 as an index. L_{net} is expressed in load units. This
load may also be specified through graphs.
For FrontAnnotation, L_{net} tables are derived from empirical
measurement of hundreds of nets of equal size in actual circuits on the
same array and the resulting 50% point in the normal distribution (the
median) is used as the table entry. This means that 50% of the net delays
computed with this number will be equal to or smaller than this number
and 50% will be equal to or larger than the computed number.
When an array is preliminary, not many circuits will have been tested
or measured. This means that the FrontAnnotation values are estimates
of expected delays. The errors could be in either direction.
For any array, FrontAnnotation accuracy decreases with net size.
Critical paths that are preplaced or given a higher priority in place
and route operations than the rest of the circuit can be kept within the
FrontAnnotation limits. Other circuits that are not critical will have
longer metal lengths.
A reasonable number of paths in the circuit can be prioritized, with
the allowed number a function of other the placement restrictions for
the circuit, cell utilization and internal pin count. A limit  on the
number of preplaced and priority routed paths  of 20% is satisfactory
for most circuits.
Preplacement should not be considered as a solution to a timing problem.
It is available as an aid, depending on other placement considerations.
FanIn
The loading that a typical macro presents to its driving source is typically
one load for bipolar arrays and higher for BiCMOS arrays. Some vendors
specify fanin in tabular form with other specification data, or indicate
a general rule.
Some macros look as if they present two or more loads to their driving
sources when they do not. The graphic representation is a logical picture
of the function, not a physical representation of how the function is
constructed.
FanOut  L_{fo}
Fanin affects the electrical loading presented to the driving macro.
The electrical fanout load count may be higher than the physical fanout
load count. For example, a pin with a fanin of 2 counts as two electrical
loads in L_{fo} and one physical pin when looking up L_{net}.
Fanout violations or fanout in excess of derated levels should have
been checked during the design review of the circuit. Derated fanout
limits are used by the AMCCERC software when performing fanout load limit
violation checking. If a fanout load is found to be excessive, the circuit
must be corrected before proceeding with the timing analysis.
L_{fo} is the sum of all fanout loads. This is the sum of all
electrical fanout loads  the sum of the fanin for each pin connected
to the net. L_{fo} is expressed in load units. The load a macro
presents to a driving macro is part of the macro specifications.
WireOR  L_{wo}
For arrays that allow wireORs, L_{wo} is W * (n1) where
W is the wireOR load factor for the array and n is the wireOR size.
L_{wo} is expressed in load units. This term only exists for those
arrays that allow a wireOR.
Not all arrays in all technologies allow the use of the wireOR. If it
is legal for the array, the presence of a wireOR in a net will affect
both the electrical and the physical loading in the net.
WireORing two outputs will not increase the fanout load limit in the
bipolar arrays as it would have in a CMOS array. AMCC Q5000 arrays, which
allow wireORs, powerdown the additional current sources by way of conditional
geometry software.
Load units for the Q5000 wireOR macros are shown in Table 52.
Example
Table 52 Q5000 WireOr Loading (L_{wo})
WIREOR SIZE 
LU 
WIREOR2 
0.40 
WIREOR3 
0.80 
WIREOR4 
1.20 
