Sizing the Design  Selecting the Array
Last Edit July 22, 2001
Array Sizing
Cell Structure
Each cell in an array consists of a number of uncommitted transistors,
resistors and other discrete components and is designed around the performance
criteria for the intended macro library. The cells will vary between array
series, regardless of the vendor.
Equivalent gates
The number of equivalent gates has been a design measure dating from
the days of discrete designs first converting into SSIlevel ICs. Integrated
circuits were classed as SSI, MSI and LSI based on their equivalent gate
counts. Circuits were "sized" based on the number of equivalent
gates it would take to create them. CMOS arrays carried on with the equivalent
gate count and it was reasonable because the internal cell in a CMOS array
can be sized as 1, 2 or 3 gates.
Bipolar arrays carry equivalent gate counts on their data sheets as a
sizing measure but it serves only to show relative sizing between
arrays in the same series. Bipolar array cell complexities render equivalent
gates a rough measure at best. BiCMOS cells are more complex than CMOS
and equivalent gate estimates are not recom mended for them either.
To complicate the problem, vendors use many different methods for computing
equiva lent gates. The designer would need the algorithms before a rational
comparison based on equivalent gates can be made between and two array
series, even from the same vendor.
Example  Method 1
One approach to array sizing is to count the number of transistors in
the internal core cells, assume that 2.5 transistors is equivalent to
a gate (Digital Equipment's defini tion), and compute the number of equivalent
gates per cell. The product of the number of cells times the number of
gates per cell provides the equivalent gates per array.
equivalent gates = ( number of transistors in core / 2.5 )
Example  Method 2
Another method is to use the D flip/flop. Sizing the D flip/flop as 11
gates, the Q20000 Series D flip/flop uses 2 internal cells.
equivalent gates = ( number of internal cells / 2 ) * 11
Example  Method 3
The usual AMCC method is to size a 3:1 MUXD flip/flop macro as 11 gates.
The Q20000 Series 3:1 MUXD flip/flop uses 3 internal cells.
equivalent gates = (number of internal cells / 3) * 11
Example  Method 4
The last method discussed here is to size a full adder at 16 gates. For
the Q20000 Series, a 1bit full adder takes 3 internal cells.
equivalent gates = (number of internal cells / 3) * 16
or:
equivalent gates = [(number of internal cells / number of cells required
for measuring function) * number of gates in function]
AMCC ASIC Product Selection Guide with Equivalent Gates Listed (1996)
AMCC ASIC PRODUCT SELECTION GUIDE
(1990's)

Part
Number 
Technology 
Equivalent
Gates
(Full Adder
Method) 
Number
of I/O 
Structured
Array Blocks 
Q20004 
1 Micron Bipolar 
671 
28 
None 
Q20010 
1 Micron Bipolar 
1469 
66 
None 
Q20025 
1 Micron Bipolar 
4032 
100 
None 
Q20045 
1 Micron Bipolar 
6782 
128 
None 
Q20080 
1 Micron Bipolar 
11242 
162 
None 
Q20120 
1 Micron Bipolar 
18777 
198 
None 
Q20P010 
1 Micron Bipolar 
928 
34 
1 GHz PLL 
Q20P025 
1 Micron Bipolar 
3120 
51 
1 GHz PLL 
Q20M100 
1 Micron Bipolar 
13475 
195 
RAM 
I/O cell contributions
None of these methods for estimating equivalent gates take the logic
capability of the interface cells into account. Some vendors do count
them in their published equivalent gate counts and others do not.
Example  AMCC cell design
AMCC cell design is optimized for MUX, latch and flip/flop implementations.
Each cell is designed to support highspeed requirements so that there
are no placement re strictions on the highspeed option macros due to
cell limitations. No power is used by a cell in its base configuration.
For the AMCC BiCMOS arrays, a cell is roughly 3 gates. For the bipolar
arrays, a logic cell is a more complex structure and varies with the series.
