Structured Design Methodology
Last Edit July 22, 2001
Compute the path propagation delay
Compute the path propagation delay for the most critical (time sensitive)
paths in the circuit. Make adjustments to the schematic in terms of macro
options for speed where needed. Does the estimated performance satisfy
the specification?

Sum of Macro 
Sum of Macro 
Path Delay = 
Intrinsic Delays + 
Extrinsic Loading 


Delays 
For the arrays that use typical specifications, be certain to use
the correct multiplication factor (WCM) for this worstcase analysis. Review
the assumptions made in establishing the multiplication factors and adjust
them if these assumptions are not expected to be met (i.e., derate the performance
by a higher factor). Some vendors call these multiplication factors "adjustment
factors". Be clear as to what is being adjusted and why.
There may be different multipliers for the different product grades,
Commercial and Military, and for different power supplies within the product
grade. The multiplier may depend on the macro type.
Many arrays are specified without worstcase timing multipliers. They
are specified with min/max ranges for each macro propagation delay. Maximum
path delay is found using the MAX data although the conditions for a maximum
propagation delay for an individual macro will vary. Minimum delays are
found using the MIN data.
Be certain that the proper fanout loading and performance specifications
are selected when doing this computation. Because of the high degree of
variation in the way a library is documented between vendors and between
array series from the same vendor, be certain that the rules regarding
the methods of specifying timing delays for the macros for the array series
selected are clearly understood.
Internal extrinsic loading delays are composed of metal load (Lnet),
electrical fanout load, the sum of all loads driven (Lfo), wireOR electrical
loading if the array allows wireORs and if one was used in the net (Lwo)
and the kfactors for each. The kfactors, expressed in ns/LU, convert
the load units into time units. Table 27 shows the extrinsic load
equations for internal nets as they are used by AMCC and other vendors.
Kfactors may be specified as tables, graphs, or broken down into parts
for temperature, voltage and processing. Check with the specific vendor.
Will the array support the maximum frequency
of operation and the critical path
performance requirements?

Table 27 Components Of Path Delay  Internal Loading
General Equation for Internal Extrinsic Delay:
No wireOR allowed:
tex = knet * Lnet+ kfo * Lfo
General Equation for Internal Extrinsic Delay:
WireOR allowed:
tex = knet * Lnet+ kfo * Lfo + kwo * Lwo
Worstcase Internal Extrinsic Delay:
For Arrays with a WorstCase Multiplier:
texwc = WCM * tex
For Arrays with no WorstCase Multiplier:
tex is already worstcase

External extrinsic loading delays are composed of the system load capacitance
and the package pin capacitance (Lcap) and the kfactor. The kfactor,
expressed in ns/pF, convert the load capacitance into time units. The
equation used by AMCC for this delay are listed in Table 28.
Table 28 Components Of Path Delay  External Loading
General Equation for External Extrinsic Delay:
tex = kcap * Lcap
Worstcase Internal Extrinsic Delay:
For Arrays with a WorstCase Multiplier:
texwc = WCM * tex
For Arrays with no WorstCase Multiplier:
tex is already worstcase

