We will discuss some guidelines for how proactive design techniques can simplify and speed up Hard IP reuse. Over the years, experience in VLSI design has taught us what to avoid in order for designs to be robust. Concepts such as synchronous vs. asynchronous designs and using Flip-Flops as opposed to latches are even taught in school as good design practices for minimizing surprises later on, for simplifying verification, testing and other issues. Such guidelines are scattered here and there in the literature but are stated concisely and collectively in the recently published RMM  which focuses strongly on Soft IP reuse. Such guidelines are not mandatory for chips to work but they do “make life easier”.
When it comes to recommending design rules, we may want to separate them into three areas of focus:
While the guidelines for robust design are based on years of
experience and, thus, on an enormous database, guidelines for reuse are
based on a relatively short period and an as yet limited number of
designs. This makes it all the more important to share what has been
learned thus far.
It is clear that the S-o-C approach will become more popular over time. While it is without a doubt a serious engineering challenge, the benefits are so great that it is too tempting to be left alone. When it happens, it will involve Soft IP and Hard IP because of the enormous investments in existing designs and the confidence that every single reused design will work. Another important issue to consider is that a lot of software, such as control software, simulation and test software, is already available and its reliability and usefulness have been established.
Finally, some Hard IP will be reused because it has to satisfy certain standards, requiring a lot of investments for recertification.
The guidelines that follow only scratch the surface, but they may prompt a more lively exchange of ideas in the future. They also are changing all the time as compaction technology and processing limits keep advancing.
How to Partition a Layout?
We have already seen how the ease of defining boundaries in the layout help when it comes to migrating hierarchically, without any gain in computational complexity to speak of or a lot of setup time. The following suggestions also help make retargeting easier:
Even if they work together in a particular application, units performing different functions should be placed in separate physical boxes in a layout. Such modular design makes it easier to “plug and play” later on. This functional separation should even be done when designing Soft IP through synthesis. We have already discussed the issue of careful placement of analog blocks. An additional precaution to be taken during the layout design phase is to introduce shielding for the analog blocks. Also, since analog drivers are more sensitive to process variations, one should allow sufficient space for their drive strength to be adjustable.
Custom Layout Design Guidelines
Give all transistors the same physical orientation, especially transistors whose performance needs to tracked. When migrating a block, design rules might resize differently in the direction of a gate and opposite to the gate direction. When a cell has transistors in both orientations, less density can be achieved during migration.
Avoid Nonportable Constructs
Butted contacts are not supported by all processes and should, therefore, be avoided. The same is true for 45 degree polygons. They are not supported by all processes.
These are guidelines that make sense to a user of compaction tools. One should use consistent layer names to avoid confusion or errors. In fact, an effort should be made to standardize a set of layer names and their numbering. It helps avoid mistakes and makes data exchange easier, especially in companies where design efforts are partitioned by using well organized hierarchical design methodologies.
To summarize, just as for any well organized design organization following proven engineering and design practices, one should systematically build up, document and disseminate guidelines learned with every project. This is no different for Hard IP reuse.