To optimize the performance of a chip, the number of physical dimensions that affect performance can be affected at different points in the process.

For the fabrication of the chips, there are all the geometrical and physical parameters that are manipulated when a chip fabrication process is designed. In general, there is a lot of talk about visible changes, such as the minimum possible channel length for a MOS transistor. However, there are many others that are constantly balanced against each other, parameters such as metal thickness, oxide thickness, metal composition to lower resistance and increase current carrying capability, the k factor of the oxide to lower capacitive coupling.

There are many more, but some of them only became important with DSM capability. So why talk about processing when the focus of our discussion is layout manipulation using compaction? The reason is that although compaction can not change processing parameters, some of the statistical feedback discussed in Chapter 2 can be used to help optimize some of their choices. We will not, however, discuss these issues further here, although it is important to know about these possibilities to facilitate cooperation between design and processing engineers.


Although, the front-end of chip design is not layout design, the information provided here is directly linked to back-end optimization. In a sense, the boundary between front-end and back-end is routing. In fact, compaction is a “silent partner” in routing for two reasons:

  1. Buffer insertions may involve both front-end and back-end (postlayout) operations. If insertion happens before or during routing, the buffer sizing is based on estimates and is a front-end procedure. If the buffer sizing stage is correct and the timing problem eliminated, compaction is unnecessary. However, since the buffer sizing stage is based on estimates, this may not happen. If the buffer size needs to be tweaked, it becomes a back-end optimization problem and is discussed in the next section.
  2. As we will discuss in this optimization chapter, the second basis for the partnership between routing and optimization is compaction, which applied to the interconnect itself, is very powerful. Compaction performed on the interconnect alone may solve many timing problems.

Inserting buffer stages into longer interconnects is an established and proven approach that is still practiced to speed up long interconnect paths [8]. Unfortunately, it adds power to already overheated chips. Selecting the best routing algorithm for a particular chip layout is another complex challenge that is getting worse with DSM. The following discussion will highlight the extreme flexibility required in routing to keep up with rapidly changing processing technologies.

The goals for floorplanning or placement for DSM processes are quite clear. Key interconnects should be as short as possible. The goals for routing are not only short key interconnects but predictable length and timing, in addition to some other requirements. This is a difficult task for a router and, since routing is one of the more compute-intensive tasks, there are limits on how many constraints can be forced on a router. And some aspects of routing are getting even more complicated than that. For instance, balancing the lengths of clock trees may not result in equal delays. Some of the criteria used for routing algorithms that yielded the highest performance chips before DSM technology are no longer satisfactory.

Extensive research into interconnect topology optimization shows that there are different “best” approaches, depending on the application and shrinking layout geometries. Obtaining an optimally laid out and routed chip is indeed a difficult and multidimensional task. The interested reader may find the following references useful for gaining an appreciation of the complexity of the problem.

The abbreviations of the titles given here are only partly indicative and largely confusing. They are names of routers, most of them the initials of their creators. They are all routing algorithms based on different cost (performance) criteria: Bounded-radius bounded-cost trees, AHHK trees, maximum performance trees, A-trees, low-delay trees, IDW/CFD trees [3], This large variety of possibilities strongly suggest that there will be room for back-end optimization for quite some time to come and that it is a constantly changing target - if, of course, you want to squeeze the maximum performance out of a chip with optimization.


It took years of painstaking research [3] to show the significance of optimizing what already seems to have been close to the optimum: A timing-driven laid-out VLSI chip. One of the key issues is that all this timing-driven work is based too extensively on statistical data, in other words on past performance. We already know what this kind of data means in the stock market. It may not be as bad for chips, but it is certainly, not perfect. Of course, progress is constantly being made.

Timing-driven approaches are getting better all the time. However, the technology keeps also advancing. As we have seen above in paragraph 3.5.1, there are plenty of routing algorithms. The best lime to truly optimize the performance of a well designed chip is when it is completely laid out. This makes perfect sense. Of course, if the timing is completely off, postlayout optimization is not going to “save the chip.”

However, it is truly amazing how much leverage is still possible at this point in time. The simplest approach in back-end “optimization” is to enlarge transistor sizes in slower paths. This is done commercially with tools such as AMPS. We discuss this tool in Chapter 6. Another approach already discussed is the insertion and optimization of buffers. Both of these approaches increase the speed of a chip at the price of increasing chip area and power consumption.

It seems that none of the commercial approaches takes the geometrical dimensions of interconnects into account. Very recent research suggests that the best results are achieved if both interconnects and the transistors driving them arc simultaneously optimized, like a matched pair. Actually two distinct approaches have been suggested. One algorithm optimizes the interconnect/transistor pair for the fastest speed irrespective of power consumption. Another algorithm optimizes speed, while at the same time minimizing power dissipation [3].

Experimental and computational results have shown substantial improvement in these vital performance parameters. The improvements are based solely on back-end optimizing, independent of improvements that can be achieved with optimal routing. Since the exact numbers are reasonably dependent on the particular application, it is adequate for this discussion to put the potential reduction in both delay and power consumption at around 50% for a path that has been optimized.

This is simply too enormpns to remain nonchalant about it!

Such results, based so far on university research, deserve serious consideration.