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Application-Specific Integrated Circuits

Michael John Sebastian Smith
ISBN 0-201-50022-1 * Hardcover * 1040 pages * 1997

Table of Contents

1 INTRODUCTION TO ASICs 1

1.1 Types of ASICs 4
1.1.1 Full-Custom ASICs 5
1.1.2 Standard-Cell-Based ASICs 6
1.1.3 Gate-Array-Based ASICs 11
1.1.4 Channeled Gate Array 12
1.1.5 Channelless Gate Array 12
1.1.6 Structured Gate Array 13
1.1.7 Programmable Logic Devices 14
1.1.8 Field-Programmable Gate Arrays 16
1.2 Design Flow 16
1.3 Case Study 18
1.4 Economics of ASICs 20
1.4.1 Comparison Between ASIC Technologies 20
1.4.2 Product Cost 20
1.4.3 ASIC Fixed Costs 21
1.4.4 ASIC Variable Costs 25
1.5 ASIC Cell Libraries 27
1.6 Summary 30
1.7 Problems 31
1.8 Bibliography 36
1.9 References 38

2 CMOS LOGIC 39

2.1 CMOS Transistors 41
2.1.1 P-Channel Transistors 45
2.1.2 Velocity Saturation 45
2.1.3 SPICE Models 47
2.1.4 Logic Levels 47
2.2 The CMOS Process 49
2.2.1 Sheet Resistance 55
2.3 CMOS Design Rules 58
2.4 Combinational Logic Cells 60
2.4.1 Pushing Bubbles 63
2.4.2 Drive Strength 65
2.4.3 Transmission Gates 66
2.4.4 Exclusive-OR Cell 69
2.5 Sequential Logic Cells 70
2.5.1 Latch 70
2.5.2 Flip-Flop 71
2.5.3 Clocked Inverter 73
2.6 Datapath Logic Cells 75
2.6.1 Datapath Elements 77
2.6.2 Adders 79
2.6.3 A Simple Example 85
2.6.4 Multipliers 87
2.6.5 Other Arithmetic Systems 94
2.6.6 Other Datapath Operators 95
2.7 I/O Cells 99
2.8 Cell Compilers 102
2.9 Summary 102
2.10 Problems 103
2.11 Bibliography 113
2.12 References 114

3 ASIC LIBRARY DESIGN 117

3.1 Transistors as Resistors 117
3.2 Transistor Parasitic Capacitance 122
3.2.1 Junction Capacitance 124
3.2.2 Overlap Capacitance 124
3.2.3 Gate Capacitance 124
3.2.4 Input Slew Rate 126
3.3 Logical Effort 129
3.3.1 Predicting Delay 134
3.3.2 Logical Area and Logical Efficiency 134
3.3.3 Logical Paths 135
3.3.4 Multistage Cells 137
3.3.5 Optimum Delay 138
3.3.6 Optimum Number of Stages 140
3.4 Library-Cell Design 141
3.5 Library Architecture 142
3.6 Gate-Array Design 144
3.7 Standard-Cell Design 150
3.8 Datapath-Cell Design 152
3.9 Summary 155
3.10 Problems 155
3.11 Bibliography 167
3.12 References 168

4 PROGRAMMABLE ASICs 169

4.1 The Antifuse 170
4.1.1 Metal-Metal Antifuse 172
4.2 Static RAM 174
4.3 EPROM and EEPROM Technology 174
4.4 Practical Issues 176
4.4.1 FPGAs in Use 177
4.5 Specifications 178
4.6 PREP Benchmarks 179
4.7 FPGA Economics 180
4.7.1 FPGA Pricing 180
4.7.2 Pricing Examples 183
4.8 Summary 184
4.9 Problems 185
4.10 Bibliography 190
4.11 References 190

5 PROGRAMMABLE ASIC LOGIC CELLS 191

5.1 Actel ACT 191
5.1.1 ACT 1 Logic Module 191
5.1.2 Shannon's Expansion Theorem 192
5.1.3 Multiplexer Logic as Function Generators 193
5.1.4 ACT 2 and ACT 3 Logic Modules 196
5.1.5 Timing Model and Critical Path 197
5.1.6 Speed Grading 201
5.1.7 Worst-Case Timing 201
5.1.8 Actel Logic Module Analysis 204
5.2 Xilinx LCA 204
5.2.1 XC3000 CLB 204
5.2.2 XC4000 Logic Block 206
5.2.3 XC5200 Logic Block 207
5.2.4 Xilinx CLB Analysis 207
5.3 Altera FLEX 209
5.4 Altera MAX 209
5.4.1 Logic Expanders 211
5.4.2 Timing Model 215
5.4.3 Power Dissipation in Complex PLDs 217
5.5 Summary 218
5.6 Problems 224
5.7 Bibliography 229
5.8 References 230

6 PROGRAMMABLE ASIC I/O CELLS 231

6.1 DC Output 232
6.1.1 Totem-Pole Output 234
6.1.2 Clamp Diodes 235
6.2 AC Output 235
6.2.1 Supply Bounce 239
6.2.2 Transmission Lines 240
6.3 DC Input 243
6.3.1 Noise Margins 244
6.3.2 Mixed-Voltage Systems 246
6.4 AC Input 248
6.4.1 Metastability 249
6.5 Clock Input 253
6.5.1 Registered Inputs 253
6.6 Power Input 255
6.6.1 Power Dissipation 256
6.6.2 Power-On Reset 258
6.7 Xilinx I/O Block 258
6.7.1 Boundary Scan 260
6.8 Other I/O Cells 261
6.9 Summary 262
6.10 Problems 263
6.11 Bibliography 272
6.12 References 273

7 PROGRAMMABLE ASIC INTERCONNECT 275

7.1 Actel ACT 275
7.1.1 Routing Resources 276
7.1.2 Elmore's Constant 278
7.1.3 RC Delay in Antifuse Connections 280
7.1.4 Antifuse Parasitic Capacitance 281
7.1.5 ACT 2 and ACT 3 Interconnect 283
7.2 Xilinx LCA 284
7.3 Xilinx EPLD 288
7.4 Altera MAX 5000 and 7000 289
7.5 Altera MAX 9000 290
7.6 Altera FLEX 291
7.7 Summary 292
7.8 Problems 294
7.9 Bibliography 297
7.10 References 297

8 PROGRAMMABLE ASIC DESIGN SOFTWARE 299

8.1 Design Systems 299
8.1.1 Xilinx 301
8.1.2 Actel 303
8.1.3 Altera 303
8.2 Logic Synthesis 304
8.2.1 FPGA Synthesis 305
8.3 The Halfgate ASIC 307
8.3.1 Xilinx 307
8.3.2 Actel 310
8.3.3 Altera 310
8.3.4 Comparison 315
8.4 Summary 316
8.5 Problems 316
8.6 Bibliography 320
8.6.1 FPGA Vendors 321
8.6.2 Third-Party Software 323
8.7 References 326

9 LOW-LEVEL DESIGN ENTRY 327

9.1 Schematic Entry 328
9.1.1 Hierarchical Design 330
9.1.2 The Cell Library 330
9.1.3 Names 332
9.1.4 Schematic Icons and Symbols 333
9.1.5 Nets 336
9.1.6 Schematic Entry for ASICs and PCBs 336
9.1.7 Connections 338
9.1.8 Vectored Instances and Buses 338
9.1.9 Edit-in-Place 340
9.1.10 Attributes 341
9.1.11 Netlist Screener 341
9.1.12 Schematic-Entry tools 343
9.1.13 Back-Annotation 345
9.2 Low-Level Design Languages 345
9.2.1 ABEL 346
9.2.2 CUPL 348
9.2.3 PALASM 350
9.3 PLA Tools 353
9.4 EDIF 355
9.4.1 EDIF Syntax 355
9.4.2 An EDIF Netlist Example 357
9.4.3 An EDIF Schematic Icon 359
9.4.4 An EDIF Example 365
9.5 CFI Design Representation 369
9.5.1 CFI Connectivity Model 370
9.6 Summary 373
9.7 Problems 373
9.8 Bibliography 376
9.9 References 377

10 VHDL 379

10.1 A Counter 380
10.2 A 4-bit Multiplier 381
10.2.1 An 8-bit Adder 381
10.2.2 A Register Accumulator 381
10.2.3 Zero Detector 383
10.2.4 A Shift Register 384
10.2.5 A State Machine 384
10.2.6 A Multiplier 385
10.2.7 Packages and Testbench 388
10.3 Syntax and Semantics of VHDL 390
10.4 Identifiers and Literals 392
10.5 Entities and Architectures 393
10.6 Packages and Libraries 398
10.6.1 Standard Package 399
10.6.2 Std_logic_1164 Package 400
10.6.3 Textio Package 402
10.6.4 Other Packages 403
10.6.5 Creating Packages 404
10.7 Interface Declarations 405
10.7.1 Port Declaration 406
10.7.2 Generics 410
10.8 Type Declarations 411
10.9 Other Declarations 413
10.9.1 Object Declarations 414
10.9.2 Subprogram Declarations 415
10.9.3 Alias and Attribute Declarations 418
10.9.4 Predefined Attributes 419
10.10 Sequential Statements 419
10.10.1 Wait Statement 421
10.10.2 Assertion and Report Statements 423
10.10.3 Assignment Statements 424
10.10.4 Procedure Call 426
10.10.5 If Statement 427
10.10.6 Case Statement 428
10.10.7 Other Sequential Control Statements 429
10.11 Operators 430
10.12 Arithmetic 432
10.12.1 IEEE Synthesis Packages 434
10.13 Concurrent Statements 437
10.13.1 Block Statement 438
10.13.2 Process Statement 440
10.13.3 Concurrent Procedure Call 441
10.13.4 Concurrent Signal Assignment 442
10.13.5 Concurrent Assertion Statement 443
10.13.6 Component Instantiation 444
10.13.7 Generate Statement 444
10.14 Execution 445
10.15 Configurations and Specifications 447
10.16 An Engine Controller 449
10.17 Summary 456
10.18 Problems 459
10.19 Bibliography 477
10.20 References 478

11 VERILOG HDL 479

11.1 A Counter 480
11.2 Basics of the Verilog Language 482
11.2.1 Verilog Logic Values 483
11.2.2 Verilog Data Types 483
11.2.3 Other Wire Types 486
11.2.4 Numbers 486
11.2.5 Negative Numbers 488
11.2.6 Strings 489
11.3 Operators 490
11.3.1 Arithmetic 492
11.4 Hierarchy 494
11.5 Procedures and Assignments 495
11.5.1 Continuous Assignment Statement 496
11.5.2 Sequential Block 497
11.5.3 Procedural Assignments 498
11.6 Timing Controls and Delay 498
11.6.1 Timing Control 498
11.6.2 Data Slip 501
11.6.3 Wait Statement 502
11.6.4 Blocking and Nonblocking Assignments 503
11.6.5 Procedural Continuous Assignment 504
11.7 Tasks and Functions 506
11.8 Control Statements 506
11.8.1 Case and If Statement 506
11.8.2 Loop Statement 507
11.8.3 Disable 508
11.8.4 Fork and Join 509
11.9 Logic-Gate Modeling 509
11.9.1 Built-in Logic Models 509
11.9.2 User-Defined Primitives 510
11.10 Modeling Delay 512
11.10.1 Net and Gate Delay 512
11.10.2 Pin-to-Pin Delay 513
11.11 Altering Parameters 515
11.12 A Viterbi Decoder 515
11.12.1 Viterbi Encoder 515
11.12.2 The Received Signal 519
11.12.3 Testing the System 521
11.12.4 Verilog Decoder Model 523
11.13 Other Verilog Features 532
11.13.1 Display Tasks 533
11.13.2 File I/O Tasks 533
11.13.3 Timescale, Simulation, and Timing-Check Tasks 534
11.13.4 PLA Tasks 537
11.13.5 Stochastic Analysis Tasks 538
11.13.6 Simulation Time Functions 539
11.13.7 Conversion Functions 539
11.13.8 Probability Distribution Functions 540
11.13.9 Programming Language Interface 541
11.14 Summary 541
11.15 Problems 543
11.15.1 The Viterbi Decoder 556
11.16 Bibliography 557
11.17 References 557

12 LOGIC SYNTHESIS 559

12.1 A Logic-Synthesis Example 560
12.2 A Comparator/MUX 561
12.2.1 An Actel Version of the Comparator/MUX 567
12.3 Inside a Logic Synthesizer 569
12.4 Synthesis of the Viterbi Decoder 572
12.4.1 ASIC I/O 572
12.4.2 Flip-Flops 575
12.4.3 The Top-Level Model 575
12.5 Verilog and Logic Synthesis 580
12.5.1 Verilog Modeling 580
12.5.2 Delays in Verilog 581
12.5.3 Blocking and Nonblocking Assignments 582
12.5.4 Combinational Logic in Verilog 582
12.5.5 Multiplexers In Verilog 584
12.5.6 The Verilog Case Statement 585
12.5.7 Decoders In Verilog 586
12.5.8 Priority Encoder in Verilog 587
12.5.9 Arithmetic in Verilog 587
12.5.10 Sequential Logic in Verilog 589
12.5.11 Component Instantiation in Verilog 590
12.5.12 Datapath Synthesis in Verilog 591
12.6 VHDL and Logic Synthesis 593
12.6.1 Initialization and Reset 593
12.6.2 Combinational Logic Synthesis in VHDL 594
12.6.3 Multiplexers in VHDL 594
12.6.4 Decoders in VHDL 595
12.6.5 Adders in VHDL 597
12.6.6 Sequential Logic in VHDL 597
12.6.7 Instantiation in VHDL 598
12.6.8 Shift Registers and Clocking in VHDL 601
12.6.9 Adders and Arithmetic Functions 603
12.6.10 Adder/Subtracter and Don't Cares 604
12.7 Finite-State Machine Synthesis 605
12.7.1 FSM Synthesis in Verilog 607
12.7.2 FSM Synthesis in VHDL 608
12.8 Memory Synthesis 611
12.8.1 Memory Synthesis in Verilog 611
12.8.2 Memory Synthesis in VHDL 612
12.9 The Multiplier 614
12.9.1 Messages During Synthesis 617
12.10 The Engine Controller 619
12.11 Performance-Driven Synthesis 620
12.12 Optimization of the Viterbi Decoder 625
12.13 Summary 628
12.14 Problems 629
12.15 Bibliography 638
12.16 References 639

13 SIMULATION 641

13.1 Types of Simulation 641
13.2 The Comparator/MUX Example 643
13.2.1 Structural Simulation 644
13.2.2 Static Timing Analysis 647
13.2.3 Gate-Level Simulation 648
13.2.4 Net Capacitance 650
13.3 Logic Systems 652
13.3.1 Signal Resolution 653
13.3.2 Logic Strength 653
13.4 How Logic Simulation Works 656
13.4.1 VHDL Simulation Cycle 658
13.4.2 Delay 658
13.5 Cell Models 659
13.5.1 Primitive Models 659
13.5.2 Synopsys Models 660
13.5.3 Verilog Models 661
13.5.4 VHDL Models 663
13.5.5 VITAL Models 664
13.5.6 SDF in Simulation 667
13.6 Delay Models 669
13.6.1 Using a Library Data Book 670
13.6.2 Input-Slope Delay Model 672
13.6.3 Limitations of Logic Simulation 674
13.7 Static Timing Analysis 675
13.7.1 Hold Time 678
13.7.2 Entry Delay 679
13.7.3 Exit Delay 680
13.7.4 External Setup Time 681
13.8 Formal Verification 682
13.8.1 An Example 682
13.8.2 Understanding Formal Verification 684
13.8.3 Adding an Assertion 685
13.8.4 Completing a Proof 687
13.9 Switch-Level Simulation 688
13.10 Transistor-Level Simulation 689
13.10.1 A PSpice Example 689
13.10.2 SPICE Models 692
13.11 Summary 696
13.12 Problems 696
13.13 Bibliography 708
13.14 References 708

14 TEST 711

14.1 The Importance of Test 712
14.2 Boundary-Scan Test 714
14.2.1 BST Cells 716
14.2.2 BST Registers 718
14.2.3 Instruction Decoder 719
14.2.4 TAP Controller 722
14.2.5 Boundary-Scan Controller 724
14.2.6 A Simple Boundary-Scan Example 727
14.2.7 BSDL 732
14.3 Faults 736
14.3.1 Reliability 736
14.3.2 Fault Models 737
14.3.3 Physical Faults 738
14.3.4 Stuck-at Fault Model 740
14.3.5 Logical Faults 741
14.3.6 IDDQ Test 742
14.3.7 Fault Collapsing 743
14.3.8 Fault-Collapsing Example 743
14.4 Fault Simulation 745
14.4.1 Serial Fault Simulation 747
14.4.2 Parallel Fault Simulation 747
14.4.3 Concurrent Fault Simulation 747
14.4.4 Nondeterministic Fault Simulation 748
14.4.5 Fault-Simulation Results 748
14.4.6 Fault-Simulator Logic Systems 749
14.4.7 Hardware Acceleration 751
14.4.8 A Fault-Simulation Example 752
14.4.9 Fault Simulation in an ASIC Design Flow 754
14.5 Automatic Test-Pattern Generation 755
14.5.1 The D-Calculus 755
14.5.2 A Basic ATPG Algorithm 757
14.5.3 The PODEM Algorithm 759
14.5.4 Controllability and Observability 761
14.6 Scan Test 764
14.7 Built-in Self-test 766
14.7.1 LFSR 766
14.7.2 Signature Analysis 766
14.7.3 A Simple BIST Example 767
14.7.4 Aliasing 768
14.7.5 LFSR Theory 771
14.7.6 LFSR Example 773
14.7.7 MISR 775
14.8 A Simple Test Example 778
14.8.1 Test-Logic Insertion 778
14.8.2 How the Test Software Works 780
14.8.3 ATVG and Fault Simulation 787
14.8.4 Test Vectors 787
14.8.5 Production Tester Vector Formats 789
14.8.6 Test Flow 791
14.9 The Viterbi Decoder Example 791
14.10 Summary 794
14.11 Problems 794
14.12 Bibliography 800
14.13 References 801

15 ASIC CONSTRUCTION 805

15.1 Physical Design 805
15.2 CAD Tools 807
15.2.1 Methods and Algorithms 808
15.3 System Partitioning 809
15.4 Estimating ASIC Size 811
15.5 Power Dissipation 816
15.5.1 Switching Current 816
15.5.2 Short-Circuit Current 817
15.5.3 Subthreshold and Leakage Current 818
15.6 FPGA Partitioning 820
15.6.1 ATM Simulator 820
15.6.2 Automatic Partitioning with FPGAs 823
15.7 Partitioning Methods 824
15.7.1 Measuring Connectivity 824
15.7.2 A Simple Partitioning Example 826
15.7.3 Constructive Partitioning 827
15.7.4 Iterative Partitioning Improvement 828
15.7.5 The Kernighan-Lin Algorithm 829
15.7.6 The Ratio-Cut Algorithm 834
15.7.7 The Look-ahead Algorithm 835
15.7.8 Simulated Annealing 836
15.7.9 Other Partitioning Objectives 837
15.8 Summary 838
15.9 Problems 838
15.10 Bibliography 850
15.11 References 851

16 FLOORPLANNING AND PLACEMENT 853

16.1 Floorplanning 853
16.1.1 Floorplanning Goals and Objectives 854
16.1.2 Measurement of Delay inFloorplanning 856
16.1.3 Floorplanning Tools 859
16.1.4 Channel Definition 861
16.1.5 I/O and Power Planning 864
16.1.6 Clock Planning 869
16.2 Placement 873
16.2.1 Placement Terms and Definitions 873
16.2.2 Placement Goals and Objectives 876
16.2.3 Measurement of Placement Goals and Objectives 877
16.2.4 Placement Algorithms 882
16.2.5 Eigenvalue Placement Example 885
16.2.6 Iterative Placement Improvement 887
16.2.7 Placement Using Simulated Annealing 890
16.2.8 Timing-Driven Placement Methods 891
16.2.9 A Simple Placement Example 893
16.3 Physical Design Flow 894
16.4 Information Formats 895
16.4.1 SDF for Floorplanning and Placement 895
16.4.2 PDEF 896
16.4.3 LEF and DEF 897
16.5 Summary 898
16.6 Problems 898
16.7 Bibliography 906
16.8 References 906

17 ROUTING 909

17.1 Global Routing 910
17.1.1 Goals and Objectives 911
17.1.2 Measurement of Interconnect Delay 912
17.1.3 Global Routing Methods 915
17.1.4 Global Routing Between Blocks 916
17.1.5 Global Routing Inside Flexible Blocks 918
17.1.6 Timing-Driven Methods 920
17.1.7 Back-annotation 921
17.2 Detailed Routing 922
17.2.1 Goals and Objectives 926
17.2.2 Measurement of Channel Density 927
17.2.3 Algorithms 928
17.2.4 Left-Edge Algorithm 928
17.2.5 Constraints and Routing Graphs 928
17.2.6 Area-Routing Algorithms 931
17.2.7 Multilevel Routing 933
17.2.8 Timing-Driven Detailed Routing 933
17.2.9 Final Routing Steps 934
17.3 Special Routing 935
17.3.1 Clock Routing 935
17.3.2 Power Routing 936
17.4 Circuit Extraction and DRC 939
17.4.1 SPF, RSPF, and DSPF 939
17.4.2 Design Checks 944
17.4.3 Mask Preparation 945
17.5 Summary 946
17.6 Problems 947
17.7 Bibliography 956
17.8 References 957

A VHDL RESOURCES 961

A.1 BNF 961
A.2 VHDL Syntax 963
A.3 BNF Index 973
A.4 Bibliography 973
A.5 References 976

B VERILOG HDL RESOURCES 979

B.1 Explanation of the Verilog HDL BNF 979
B.2 Verilog HDL Syntax 980
B.3 BNF Index 994
B.4 Verilog HDL LRM 994
B.5 Bibliography 997
B.6 References 999

GLOSSARY 1000

INDEX 1006
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