16.3 Physical Design Flow
Historically placement was included with routing as a single tool (the term
is often used for place and route). Because interconnect delay now dominates gate delay, the trend is to include placement within a floorplanning tool and use a separate router.
design flow using synthesis and a floorplanning tool that includes placement. This flow consists of the following steps:
The input is a logical description with no physical information.
The initial synthesis contains little or no information on any interconnect loading. The output of the synthesis tool (typically an EDIF netlist) is the input to the floorplanner.
From the initial floorplan interblock capacitances are input to the synthesis tool as load constraints and intrablock capacitances are input as wire-load tables.
Synthesis with load constraints.
At this point the synthesis tool is able to resynthesize the logic based on estimates of the interconnect capacitance each gate is driving. The synthesis tool produces a forward annotation file to constrain path delays in the placement step.
Timing-driven floorplanning and placement design flow. Compare with Figure 15.1 on p. 806.
After placement using constraints from the synthesis tool, the location of every logic cell on the chip is fixed and accurate estimates of interconnect delay can be passed back to the synthesis tool.
). The synthesis tool changes the drive strength of gates based on the accurate interconnect delay estimates from the floorplanner without altering the netlist structure.
The placement information is ready to be input to the routing step.
we iterate between floorplanning and synthesis, continuously improving our estimate for the interconnect delay as we do so.
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