14.11  Problems

* = Difficult, ** = Very difficult, *** = Extremely difficult

14.1 (Acronyms, 10 min.) Translate the following excerpt from a MOSIS report: “Chip description: DLX RISC ASIC with DFT, IEEE 1149 BST, and BIST using PRBS LFSR and MISR. Test results: compaction shorted words.”

14.2  (Economics of defect levels, 15 min.) You are the product manager for a new workstation. You use 10 similar ASICs as the key component in a computer that sells for $10,000 with a profit margin of 20 percent. You buy the ASICs for $10 each, and the shipping defect level is certified to be 0.1 percent by the ASIC vendor. You are having a problem with a large number of field failures, which you have traced to one of the ASICs. In the first nine months of shipment you have sold 49,500 computers, but 51 have failed in the field, 26 due to the ASIC. Finance estimates that all the field failures have cost at least $1 million in revenue and goodwill. You do not have the time, money, or capability to improve your incoming inspection or assembly tests. You estimate the product lifetime is another 18 months, in which time you will sell another 50,000 units at roughly the same price and profit margin. At an emergency meeting, the ASIC vendor’s test engineer proposes to reduce the ASIC defect level to 0.01 percent immediately by improving the test program, but at a cost. You suggest a coffee break. With the information that you have, you have 15 minutes to estimate just how much extra you are prepared to pay for each ASIC.

14.3  (Defect level, 10 min.) In a series of experiments a customer of Zycad, which makes hardware fault-simulation accelerators, tested 10,000 parts from a lot with 30 percent yield. Each experiment used a different fraction of the test vector set. Fit the data in Table 14.24 to a model.

TABLE 14.24  Defect level as a function of fault coverage (Problem 14.3 ).

Fault coverage/%

Rejects

Defective parts

Defect level/%

50

6773

227

7

90

6877

133

3

99

6910

90

1

99.99

6997

3

0.01

14.4  (Test cost, 5 min.) Suppose, in the example of Section 14.1 , reducing the bASIC defect level to 0.1 percent added an extra cost of $1 to each part. Now what is the best way to build the system?

14.5 (Defects, 5 min.) Finding defects in an ASIC is a hard problem. The average defect density for a submicron process is 1 cm –2 or less.

  • a. On average how many defects are there on a 1 cm chip?
  • b. If the average defect is 1 l 2 , and l = 0.25 m m, what is defect area/chip area?
  • c. Estimate the ratio of needle volume to haystack volume and comment.

14.6 (Faults and nodes, 10 min.)

  • a. How many faults are there in a circuit with n nodes?
  • b. Considering fanout how many collapsed faults are there?
  • c. Estimate how many test cycles a fault simulator needs to find these faults.
  • d. With a 10 MHz clock, how long is a 100 k-gate test (with your estimates)?
  • e. Using a 100 MHz computer, how long does this fault simulation take? (Assume simulation time is four orders of magnitude slower than real time.)

14.7 (PRBS, 10 min.) What are the first three patterns for a 4-bit maximal-length LFSR, given a seed of '0001'? Hint: Is there more than one answer?

14.8 (Test time, 10 min.)

  • a. How long does a 16-bit shift-register test take at a clock speed of 1 MHz?
  • b. Estimate how long it takes to test a 64 k-bit static RAM using a walking 1’s (or marching 1’s) pattern.

14.9 (Test time, 10 min.) A modern production tester costs $5–10 million. This cost is depreciated over the life of the tester (usually five years in the United States due to Internal Revenue Service guidelines).

  • a. If the tester is in use 24 hours a day, 365 days a year, how much does 1 second of test time cost?
  • b. If, due to down time (maintenance, operator sick time and so on) a $10 million tester is actually in use 50 percent of the time for chip testing and test time is 2 seconds, how much does test add to the cost of an ASIC?
  • c. Suppose the ASIC die is 300 mils on a side, is fabricated on a 6-inch wafer whose fabrication cost is $1750, and the yield is 68 percent. What is the fraction of test cost to total die cost (fabrication plus test costs)? Assume that the number of die per wafer is equal to wafer area divided by chip area.

14.10  (Fault collapsing, 10 min.) Draw up tables to show how input and output faults collapse using gate collapsing for the following primitive logic gates: AND, OR, NAND, NOR, and EXOR (assume two-input logic cells in each case with inputs A, B and output F); a two-input MUX (inputs S0, S1, and SEL0; output F).

14.11  (Fault simulation, 15 min.) Mentor Graphic Corporation’s QuickFault concurrent fault simulator uses a 12-state logic system with three logic values ('0', '1', 'X') and four strengths (strong = S, resistive = R, high impedance = Z, I = indeterminate). Complete Table 14.25 using D = detected fault, P = possibly detected fault, and '–' = undetected fault. Give two values, 1/2, for each cell: The first value is for the default fault model in which a tester cannot tell the difference between Z/S/R; the second value is for testers that can differentiate between Z and S/R. Hint: One line of the table has been completed as an example.

TABLE 14.25  The logic system used by Mentor Graphic Corporation’s fault simulator, QuickFault (Problem 14.11 ). 1

 

Faulty circuit

 

 

0I

XI

1I

0Z

XZ

1Z

0R

XR

1R

0S

XS

1S

Good circuit

0I

 

 

 

 

 

 

 

 

 

 

 

 

XI

 

 

 

 

 

 

 

 

 

 

 

 

1I

 

 

 

 

 

 

 

 

 

 

 

 

0Z

 

 

 

 

 

 

 

 

 

 

 

 

XZ

 

 

 

 

 

 

 

 

 

 

 

 

1Z

–/P

–/P

–/P

–/D

–/D

–/D

–/D

–/D

–/D

0R

 

 

 

 

 

 

 

 

 

 

 

 

XR

 

 

 

 

 

 

 

 

 

 

 

 

1R

 

 

 

 

 

 

 

 

 

 

 

 

0S

 

 

 

 

 

 

 

 

 

 

 

 

XS

 

 

 

 

 

 

 

 

 

 

 

 

1S

 

 

 

 

 

 

 

 

 

 

 

 

14.12  (Finding faults, 30 min.)

  • a. List all the possible stuck-at faults for the circuit in Figure 14.37 using node faults.
  • b. Find all of the equivalent fault classes using node collapsing.
  • c. List the prime faults.
  • d. List all possible stuck-at faults using input and output faults (use A1.B and A2.B to distinguish between different inputs and outputs on the same net).
  • FIGURE 14.37  An example circuit for fault collapsing (Problem 14.12 ).

     

  • e. List the fault-equivalence classes using gate collapsing.
  • f. List the prime faults.

14.13 (Blind faith, 10 min.) Consider the following code: a = b && f(c) . Verilog stops executing an expression as soon as it determines that the expression is false, whereas VeriFault does not. What effect does this have?

14.14  (Fault collapsing, 10 min.) Draw the Karnaugh maps including stuck-at faults for four-input NAND, AND, OR, and NOR gates.

14.15 (Fault dominance, 10 min.) If T x is the set of test vectors that test for fault x and T b Õ T a , what can you say about faults a and b ?

14.16 (*Fault dominance, 10 min.) Consider the network C = AND (A, B), D = NOT (B). List the PIs, POs, and faults under a pin-fault model. For each fault, state whether it is an equivalent fault, dominant fault, or dominated fault. Now consider this more formal definition of fault dominance: Fault a dominates b if and only if a and b are equivalent under the set of tests T for b . Two faults are equivalent under a test T if and only if the circuit response of the two faulty circuits is identical. Hint: Consider the fault at the input of the inverter very carefully.

14.17 (Japanese TVs, 20 min.) As an experiment a Japanese manufacturer decided not to perform any testing of its TVs before turning them on at the end of the production line. They achieved over a 90 percent turn-on rate. Build a cost model for this approach to testing. Make a one-page list of its advantages and disadvantages.

14.18 (Test costs, 20 min.) The CEO of an ASIC vendor called a meeting and asked the production manager to bring all wafers queued for rework. The CEO produced a hammer and smashed the several hundred wafers on the boardroom table. Construct a model around the following assumptions: 2 percent of wafers-in-process currently require rework after each of the 12 photo steps in the process, wafer cost is $2 ,000, 30 percent of the wafer costs are in the photo steps; current process yield is 85 percent, 30 percent of the reworked wafers have to be scrapped. Explain why you were not as shocked by this episode as the production manager and how it helped you to explain to the CEO the need to add time to your ASIC design schedule to include design for test.

14.19 (ZyCAD RP, 10 min.) The ZyCAD Paradigm RP rapid prototyping system consists of a set of emulation boards. Each emulation board contains 18 Xilinx 3090 chips and 16 Xilinx 4010 chips. The Xilinx 4010 chips are mounted on eight daughterboards, and the 3090 chips are mounted directly on the motherboard. The Xilinx 4010 chips are used for logic block emulation and the Xilinx 3090 chips are used for crossbar routing. Each daughterboard has 288 I/O pins that are available to the crossbar chips for routing. Each Xilinx 4010 device has the capability to interface with any other 4010 device on the emulation board. The Xilinx 4010 devices have 400 Configurable Logic Blocks (CLBs) per device and 160 programmable I/O's. Estimate the size of an ASIC that you could prototype with this system.

14.20 (IDDQ testing, 10 min.) In the six-shorts-per-transistor fault model for IDDQ testing we model six shorts per transistor. What are they?

14.21  (PRBS) Consider Table 14.26 .

  • a. (15 min.) What is the autocorrelation function for a maximal-length pseudorandom binary sequence?
  • b. ** (30 min.) Suppose we apply a pseudorandom sequence to a linear system. What is its response?
  • c. *** (60 min.) Suppose we correlate this response with the original pseudorandom sequence delayed by n cycles. What is this correlation function?
  • TABLE 14.26  Autocorrelation of pseudorandom binary sequences (Problem 14.21 ).

     

    Delay (clock ticks)

     

    0

    1

    2

    3

    4

    5

    6

     

    Q2 t

    Q2 t – 1

    Q2 t – 2

    Q2 t – 3

    Q2 t – 4

    Q2 t – 5

    Q2 t – 6

     

    1

    0

    1

    0

    0

    1

    1

     

    1

    1

    0

    1

    0

    0

    1

     

    1

    1

    1

    0

    1

    0

    0

     

    0

    1

    1

    1

    0

    1

    0

     

    0

    0

    1

    1

    1

    0

    1

     

    1

    0

    0

    1

    1

    1

    0

     

    0

    1

    0

    0

    1

    1

    1

     

     

     

     

     

     

     

     

    Correlation with Q2 t

    4

    2

    2

    2

    2

    2

    2

14.22 (Sentry, 20 min.) Write a Sentry test file to check the preset of a D flip-flop.

14.23 (Synthesis, 20 min.) Consider the following equations:

f1 = x1'x2' + y3; f2 = x1x2' + x1'x2 = y2; f3 = x1x2y2' + x1'x2' = y3

How many untestable stuck-at faults are there in this network?  Suppose we simplify the logic to the following:

f1* = y2'; f2* = x1x2' + x1'x2

How many untestable stuck-at faults are there? Hint: If you are stuck, see [Bartlett et al., 1988; Brayton, Hachtel, and Sangiovanni-Vincentelli, 1990].

14.24 (Threegates, 30 min.) Recreate the Threegates example.

14.25 (LFSR) Determine the pattern sequence generated by the 4-bit LFSR shown in Figure 14.38 . Use the same format as Table 14.10 .

FIGURE 14.38  A 4-bit linear feedback shift register (LFSR) (Problem 14.25).

 

14.26  (BIST, 15 min.) Find the signature if the CUT of Figure 14.25 is Z = A'B + AC.


1. D = detected; P = possibly detected; '–' = undetected; x/y means x is the result of the default detection mechanism and y is the result when three-state detection is enabled (allowing the detection of the difference between Z and R/S strength).


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