# 13.6  Delay Models

We shall use the term timing model to describe delays outside logic cells and the term delay model to describe delays inside logic cells. These terms are not standard and often people use them interchangeably. There are also different terms for various types of delay:

• A pin-to-pin delay is a delay between an input pin and an output pin of a logic cell. This usually represents the delay of the logic cell excluding any delay contributed by interconnect.
• A pin delay is a delay lumped to a certain pin of a logic cell (usually an input). This usually represents the delay of the interconnect, but may also represent the delay of the logic cell.
• A net delay or wire delay is a delay outside a logic cell. This always represents the delay of interconnect.

In this section we shall focus on delay models and logic cell delays. In Chapter 3 we modeled logic cell delay as follows (Eq. 3.10):

 t PD = R ( C out + C p ) + t q . (13.5)

A linear delay model is also known as a prop–ramp delay model , because the delay comprises a fixed propagation delay (the intrinsic delay) and a ramp delay (the extrinsic delay). As an example, the data book entry for the inverter, cell in01d0 , in a 0.8 m m standard-cell library gives the following delay information (with delay measured in nanoseconds and capacitance in picofarads):

 RISE = 0.10 + 0.07 + (1.75 ¥ Cld) FALL = 0.09 + 0.07 + (1.95 ¥ Cld) (13.6)

RISE = 0.10 + 0.07 + (1.75 ¥ Cld) FALL = 0.09 + 0.07 + (1.95 ¥ Cld) (13.5)

The first two terms in each of these equations represents the intrinsic delay, with the last term in each equation representing the extrinsic delay. We see that the Cld corresponds to C out , R pu = 1.75 k W , and R pd = 1.95 k W ( R pu is the pull-up resistance and R pd is the pull-down resistance) .

From the data book the pin capacitances for this logic cell are as follows:

 pin I (input) = 0.060 pF pin ZN (output) = 0.038 pF (13.7)

pin I (input) = 0.060 pF pin ZN (output) = 0.038 pF (13.6)

Thus, C p = 0.038 pF and we can calculate the component of the intrinsic delay due to the output pin capacitance as follows:

 C p ¥ R pu = 0.038 ¥ 1.75 = 0.0665 ns and C p ¥ R pd = 0.038 ¥ 1.95 = 0.0741 ns (13.8)

C p ¥ R pu = 0.038 ¥ 1.75 = 0.0665 ns and C p ¥ R pd = 0.038 ¥ 1.95 = 0.0741 ns(13.7)

Suppose t qr and t qf are the parasitic delays for the rising and falling waveforms respectively. By comparing the data book equations for the rise and fall delays with Eq.  and 13.7 , we can identify t qr = 0.10 ns and t qf = 0.09 ns.

Now we can explain the timing section of the in01d0 model ( Section 13.5.3 ),

specify specparam

InCap3 = 0.060, OutCap = 0.038, MaxLoad = 1.538,

R_Ramp3 = 0.542:0.980:1.750, F_Ramp3 = 0.605:1.092:1.950;

specparam cell_count = 1.000000; specparam Transistors = 4 ;

specparam Power = 1.400000; specparam MaxLoadedRamp = 3 ;

(i=>zn)=(0.031:0.056:0.100, 0.028:0.050:0.090);

The parameter OutCap is C p . The maximum value of the parameter R_Ramp3 is R pu , and the maximum value of parameter F_Ramp3 is R pd . Finally, the maximum values of the fixed-delay triplets correspond to t qr and t qf .

## 13.6.1 Using a Library Data Book

ASIC library data books typically contain two types of information for each cell in the library—capacitance loading and delay. Table 13.7 shows the input capacitances for the inverter family for both an area-optimized library (small) and a performance-optimized library (fast).

From Table 13.7 , the input capacitance of the small library version of the inv1 (a 1X inverter gate) is 0.034 pF. Any logic cell that is driving an inv1 from the small library sees this as a load capacitance. This capacitance consists of the gate capacitance of a p -channel transistor, the gate capacitance of an n -channel transistor, and the internal cell routing. Similarly, 0.145 pF is the input capacitance of a fast inv1 . We can deduce that the transistors in the fast library are approximately 0.145 / 0.034 ⊕ 4 times larger than those in the small version. The small library and fast library may not have the same cell height (they usually do not), so that we cannot mix cells from different libraries in the same standard-cell area.

 TABLE 13.7  Input capacitances for an inverter family (pF).1 Library inv1 invh 1 invs inv8 inv12 Area 0.034 0.067 0.133 0.265 0.397 Performance 0.145 0.292 0.584 1.169 1.753

The delay table for a 2:1 MUX is shown in Table 13.8 . For example, DO/ to Z/ , indicates the path delay from the DO input rising to the Z output rising. Rising delay is denoted by '/' and falling delay by '\' .

 TABLE 13.8  Delay information for a 2:1 MUX. Propagation delay Area Performance From input 2 To output Extrinsic / nspF –1 Intrinsic / ns Extrinsic / ns Intrinsic / ns D0\ Z\ 2.10 1.42 0.5 0.8 D0/ Z/ 3.66 1.23 0.68 0.70 D1\ Z\ 2.10 1.42 0.50 0.80 D1/ Z/ 3.66 1.23 0.68 0.70 SD\ Z\ 2.10 1.42 0.50 0.80 SD\ Z/ 3.66 1.09 0.70 0.73 SD/ Z\ 2.10 2.09 0.5 1.09 SD/ Z/ 3.66 1.23 0.68 0.70

Both intrinsic delay and extrinsic delay values are given in Table 13.8 . For example, the delay t PD (from DO\ to Z \) of a 2:1 MUX from the small library is

 t PD = 1.42 ns + (2.10 ns/pF) ¥ C L (pF) . (13.9)

ASIC cell libraries may be characterized and the delay information presented in several ways in a data book. Some manufacturers simulate under worst-case slow conditions (4.5 V, 100 °C, and slow process conditions, for example) and then derate each delay value to convert delays to nominal conditions (5.0 V, 25 °C, and nominal process). This allows nominal delays to be used in the data book while maintaining accurate predictions for worst-case behavior. Other manufacturers characterize using nominal conditions and include worst-case values in the data book. In either case, we always design with worst-case values. Data books normally include process, voltage, and temperature derating factors as tables or graphs such as those shown in Tables 13.9 and 13.10 .

For example, suppose we are measuring the performance of an ASIC on the bench and the lab temperature (25 °C) and the power supply voltage (5 V) correspond to nominal operating conditions. We shall assume, in the absence of other information, that we have an ASIC from a nominal process lot. We have data book values given as worst case (worst-case temperature, 100 °C; worst-case voltage, 4.5 V; slow process) and we wish to find nominal values for delay to compare them with our measured results. From Table 13.9 the derating factor from nominal process to slow process is 1.31. From Table 13.10 the derating factor from 100 °C and 4.5 V to nominal (25 °C and 5 V) is 1.60. The derating factor from nominal to worst-case (data book values) is thus:

 worst-case = nominal ¥ 1.31 (slow process) ¥ 1.60 (4.5 V, 100 °C). (13.10)

worst-case = nominal ¥ 1.31 (slow process) ¥ 1.60 (4.5 V, 100 °C).(13.8)

To get from the data book values to nominal operating conditions we use the following equation:

 nominal = worst-case/(1.31 ¥ 1.60) = 0.477 ¥ worst-case. (13.11)

nominal = worst-case/(1.31 ¥ 1.60) = 0.477 ¥ worst-case. (13.9)

 TABLE 13.9  Process derating factors. TABLE 13.10  Temperature and voltage derating factors. Process Derating factor Supply voltage Slow 1.31 Temperature/°C 4.5V 4.75V 5.00V 5.25V 5.50V Nominal 1.0 –40 0.77 0.73 0.68 0.64 0.61 Fast 0.75 0 1.00 0.93 0.87 0.82 0.78 25 1.14 1.07 1.00 0.94 0.90 85 1.50 1.40 1.33 1.26 1.20 100 1.60 1.49 1.41 1.34 1.28 125 1.76 1.65 1.56 1.47 1.41

## 13.6.2 Input-Slope Delay Model

It is increasingly important for submicron technologies to account for the effects of the rise (and fall) time of the input waveforms to a logic cell. The nonlinear delay model described in this section was developed by Mike Misheloff at VLSI Technology and then at Compass. There are, however, no standards in this area—each ASIC company has its own, often proprietary, model.

We begin with some definitions:

• D t 0 is the time from the beginning of the input to beginning of the output.
• D t 1 is the time from the beginning of the input to the end of the output.
• I R is the time from the beginning to the end of the input ramp.

In these definitions “beginning” and “end” refer to the projected intersections of the input waveform or the output waveform with V DD and V SS as appropriate. Then we can calculate the delay, D (measured with 0.5 trip points at input and output), and output ramp, O R , as follows:

 D = ( D t 1 + D t 0 – I R ) / 2 (13.12) and O R = D t 1 – D t 0 . (13.13)

Experimentally we find that the times, D t 0 and D t 1 , are accurately modeled by the following equations:

 D t 0 = A 0 + D 0 C L + B ¥ min ( I R , C R ) + Z ¥ max (0, I R – C R ) (13.14) and D t 1 = A 1 + B I R + D 1 C L . (13.15)

C R is the critical ramp that separates two regions of operation, we call these slow ramp and fast ramp. A sensible definition for C R is the point at which the end of the input ramp occurs at the same time the output reaches the 0.5 trip point. This leads to the following equation for C R :

 A 0 + A 1 + ( D 0 + D 1 ) C L C R = –––––––––––––––––––––– (13.16) 2 (1 – B )

It is convenient to define two more parameters:

 d A = A 1 – A 0 and d D = D 1 – D 0 . (13.17)

In the region that C R > I R , we can simplify Eqs.  13.14 and by using the definitions in Eq.  13.17 , as follows:

 D = ( D t 1 + D t 0 – I R )/2 = A 0 + D 0 C L + d A /2 + d D C L /2 (13.18) and O R = D t 1 – D t 0 = d A + d D C L . (13.19)

Now we can understand the timing parameters in the primitive model in Section 13.5.1 . For example, the following parameter, tA1D_fr , models the falling input to rising output waveform delay for the logic cell (the units are a consistent set: all times are measured in nanoseconds and capacitances in picofarads):

A0 = 0.0015;dA = 0.0789;D0 = -0.2828;dD = 4.6642;B = 0.6879;Z = 0.5630;

The input-slope model predicts delay in the fast-ramp region, D ISM (50 %, FR), as follows (0.5 trip points):

 D ISM (50 %, FR) = A 0 + D 0 C L + 0.5 O R = A 0 + D 0 C L + d A /2 + d D C L /2 = 0.0015 + 0.5 ¥ 0.0789 + (–0.2828 + 0.5 ¥ 4.6642) C L = 0.041 + 2.05 C L . (13.20)

We can adjust this delay to 0.35/0.65 trip points as follows:

 D ISM (65 %, FR) = A 0 + D 0 C L + 0.65 O R = 0.0015 + 0.65 ¥ 0.0789 + ( –0.2828 C L + 0.65 ¥ 4.6642) C L = 0.053 + 2.749 C L . (13.21)

We can now compare Eq.  13.21 with the prop–ramp model. The prop–ramp parameters for this logic cell (from the primitive model in Section 13.5.1 ) are:

tA1D_fr = |( Rec prop = 0.078; ramp = 2.749; End);

These parameters predict the following prop–ramp delay (0.35/0.65 trip points):

 D PR (65 %) = 0.078 + 2.749 C L . (13.22)

The input-slope delay model and the prop–ramp delay model predict similar delays in the fast-ramp region, but for slower inputs the differences can become significant.

## 13.6.3  Limitations of Logic Simulation

Table 13.11 shows the switching characteristics of a two-input NAND gate (1X drive) from a commercial 1 m m gate-array family. The difference in propagation delay (with FO = 0) between the inputs A and B is

(0.25 – 0.17) ¥ 2 / (0.25 + 0.17) = 38 %.

This difference is taken into account only by a pin-to-pin delay model.

 TABLE 13.11  Switching characteristics of a two-input NAND gate. Fanout 3 Symbol Parameter FO = 0 /ns FO = 1 /ns FO = 2 /ns FO = 4 /ns FO = 8 /ns K /nspF –1 t PLH Propagation delay, A to X 0.25 0.35 0.45 0.65 1.05 1.25 t PHL Propagation delay, B to X 0.17 0.24 0.30 0.42 0.68 0.79 t r Output rise time, X 1.01 1.28 1.56 2.10 3.19 3.40 t f Output fall time, X 0.54 0.69 0.84 1.13 1.71 1.83

Timing information for most gate-level simulators is calculated once, before simulation, using a delay calculator. This works as long as the logic cell delays and signal ramps do not change. There are some cases in which this is not true. Table 13.12 shows the switching characteristics of a half adder. In addition to pin-to-pin timing differences there is a timing difference depending on state. For example, the pin-to-pin timing from input pin A to the output pin S depends on the state of the input pin B. Depending on whether B = '0' or B = '1' the difference in propagation delay (at FO = 0) is

(0.93 – 0.58) ¥ 2 / (0.93 + 0.58) = 46 %.

This state-dependent timing is not taken into account by simple pin-to-pin delay models and is not accounted for by most gate-level simulators.

 TABLE 13.12  Switching characteristics of a half adder. Fanout Symbol Parameter FO = 0 /ns FO = 1 /ns FO = 2 /ns FO = 4 /ns FO = 8 /ns K /nspF –1 t PLH Delay, A to S (B = '0') 0.58 0.68 0.78 0.98 1.38 1.25 t PHL Delay, A to S (B = '1') 0.93 0.97 1.00 1.08 1.24 0.48 t PLH Delay, B to S (B = '0') 0.89 0.99 1.09 1.29 1.69 1.25 t PHL Delay, B to S (B = '1') 1.00 1.04 1.08 1.15 1.31 0.48 t PLH Delay, A to CO 0.43 0.53 0.63 0.83 1.23 1.25 t PHL Delay, A to CO 0.59 0.63 0.67 0.75 0.90 0.48 t r Output rise time, X 1.01 1.28 1.56 2.10 3.19 3.40 t f Output fall time, X 0.54 0.69 0.84 1.13 1.71 1.83

1. 1Suffix '1' denotes normal drive strength, suffix 'h' denotes high-power drive strength (approximately ¥ 2) , suffix 's' denotes superpower drive strength (approximately ¥ 4), and a suffix ' m ' ( m =8 or 12) denotes inverter blocks containing m inverters.

2. / = rising and \ = falling.

3. FO = fanout in standard loads (one standard load = 0.08 pF). Nominal conditions: V DD = 5 V, T A = 25 °C.

4. FO = fanout in standard loads (one standard load = 0.08 pF). Nominal conditions: V DD = 5 V, T A = 25 °C.