9.4 (Minitutorial, 60 min.) Write a minitutorial (no more than five pages) that explains how to set up your system (location and nature of any start-up files such as .ini files for Viewlogic and so on); how to choose or change a library (for cell icons); how to choose cells, instantiate, label, and connect them; how to select, copy and delete symbols; and how to save a schematic. Use a single inverter connected to an input and output pad as an example.
9.5 (Icons, 30 min.) With an example show how to edit and create a symbol icon. Make a triangular icon (the same size as an inverter in your library but without a bubble) for a series connection of two inverters and call it myBuffer .
9.7 (VDD and VSS, 30 min.) Using a simple example of two inverters (one with input connected to VDD, the other with input connected to VSS or GND) explain how your schematic-entry system handles global power and ground nets and their connection to cell pins. Can you connect VDD or VSS to an output pin in your system? If your schematic software has a netlist screener, try it on this example.
9.8 (Hierarchy, 30 min.) Create a very simple hierarchical cell. The lowest level, named bottom , contains a single inverter (named invB ). The highest level, called top , contains another inverter, invT , whose input is connected to the output of cell bottom . Write out the netlist (in internal and EDIF format) and explain how the tool labels a hierarchical cell.
9.10 (Dangling wires, 30 min.) Create a cell, dangle1 , containing two inverters, inv1 and inv2 . Connect the input of inv1 to an external connector, in1 , and the output of inv2 to an external connector out2 . Write the netlist and explain what happens to the unlabeled and unused nets. If you have a netlist screener, run it on this example.
9.11 (PLD languages, 60 min.) Conduct a Web search on ABEL, CUPL, or PALASM (start by searching for “Logical Devices” not “ABEL”). Try and find examples of these files and write an explanation of their function using the descriptions of these languages in this chapter.
9.12 (EDIF 3 0 0, 10 min.) Download the EDIF 3 0 0 example schematic file from http://www.edif.org/edif/workshop.edf and see if your EDIF reader will accept it. What is it?
9.13 (EXPRESS-G, 15 min.) Draw an EXPRESS-G diagram for the government of your country. For example, in the United States you would start with the president and the White House and work down through the House and Senate, showing the senators and congressional representatives. In the United Kingdom you would draw the prime minister, the House of Commons, and House of Lords with the various MPs.
9.14 (ABEL PCI Target) (10 min.) Download the Xilinx Application Note, Designing Flexible PCI Interfaces with Xilinx EPLDs, January 1995 ( pci_epld.pdf at www.xilinx.com ). The Appendix of this App. Note contains the ABEL source code for a PCI Bus Interface Target. The code is long but straightforward; most of it describes the next-state transitions for the bus-controller state machine. Extract the ABEL source code using Adobe Acrobat. Hint: This is not easy; Acrobat does a poor job of selecting text; you will lose many semicolons at the end of lines that you will have to add by hand. Use Replace... to search for end-of-line, "^p" , and replace by " ; ^p" in Word. (60 min.+) Try to convert this code to a system where you can compile it. You may need conversion utilities to do this. For example Altera ( www.altera.com ) has utilities ( EAU018.EXE and EAU019.EXE located at ftp.altera.com/pub ) to convert from ABEL 4.0 to AHDL.
9.15 (CUPL, 60 min.) Download and install the CUPL demonstration package from http://www.protel.com/download.htm . Write a two-page help sheet on what you did, where the software is installed, and how to run it.
9.16 (PALASM) (30 min.) Download and install PALASM4 v1.5 from the AMD Web site at ftp://ftp.amd.com/pub/pld/software/palasm .
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