7.8  Problems

* = Difficult, ** = Very difficult, *** = Extremely difficult

7.1  (*Xilinx interconnect, 120 min.)

  • a. Write a minitutorial (one or two pages) explaining what you need to know to run and use the XACT delay calculator. Explain how to choose the part, set the display preferences, make connections to CLBs and the interconnect, and obtain timing figures.
  • b. Use the XACT editor to determine typical delays using the longlines, a switch matrix, the PIPs, and BIDI buffers (see the Xilinx data book for more detailed explanations of the interconnect structure). Draw six different typical paths using these elements and show the components of delay. Include screen shots showing the layout of the paths and cells with detailed explanations of the figures.
  • c. Construct a path using the TBUFs, the three-state buffers, driving a longline (do not forget the pull-up). Show the XACT calculated delay for your path and explain the number from data book parameters (list them and the page number from the data book).
  • d. Extend one simple path to the I/O and explain the input and output timing, again using the data book.
  • e. Include screen shots from the layout editor showing you example paths.
  • f. Bury all the ASCII (but not binary) files you used and the tools produced inside your report using “Hidden Text.” Include explanations as to what these files are and which parts of the report they go with. This includes any schematic files, netlist files, and all files produced by the Xilinx tools. Use a separate directory for this problem and make a list in your report of all files (binary and ASCII) with explanations of what each file is.

7.2 (*Actel interconnect, 120 min.) Use the Actel chip editor to explore the properties of the interconnect scheme in a similar fashion to Problem  7.1 with the following changes: in part b make at least six different paths using various antifuse connections and explain the numbers from the delay calculator. Omit part c.

7.3 (*Altera MAX interconnect, 120 min.) Use the Altera tools to determine the properties of the MAX or FLEX interconnect in a similar fashion to Problem  7.1 with the following changes: In parts b and c construct at least six example circuits that show the various paths through the FastTrack or PIA chip-level interconnect, the local LAB array, the LAB, and the macrocells.

7.4 (**Custom ASICs, 120 min.)

  • a. Write a minitutorial (one or two pages) explaining how to run an ASIC tool (Compass/Mentor/Cadence/Tanner). Enter a simple circuit (using schematic entry or synthesis and cells from a cell library) and obtain a delay estimate.
  • b. Construct at least six example circuits that show various logic paths using various logic cells (for example: an inverter, a full adder).
  • c. Perform a timing simulation (either using a static timing verifier or using a logic simulator). Compare your results with those from a data book.
  • d. Extract the circuit to include the parasitic capacitances from layout in your circuit netlist and run a simulation to predict the delays.
  • e. Compare the results that include routing capacitance with the data book values for the logic cell delays and with the values predicted before routing.
  • f. Extend one simple path to the outputs of the chip by including I/O pads in your circuit and explain the input and output timing predictions.
  • g. Bury the ASCII files you used and the tools produced inside your report.

7.5 (**Actel stubs, 60 min.)

  • a. Which metal layers do you think Actel assigns to the horizontal and vertical interconnect in the ACT 1–3 architectures and why?
  • b. Why do the ACT 1–3 input stubs not extend over more than two channels above and below the Logic Modules, since this would reduce the need for LVTs?
  • c. The ACT 2 data sheet describes the output stubs as “twisted” (or interwoven) so that they occupy only four tracks. Show that the stubs occupy four vertical tracks whether they are twisted or not.
  • d. Suggest the real reason for the twisted stubs.

7.6  (A three-input NAND in ACT 1, 30 min.) The macros that require two ACT 1 modules include the three-input NAND (others include four-input NAND, AND, NOR).

  • a. What is the problem with trying to implement a three-input NAND gate using the Actel ACT 1 Logic Module?
  • b. Suggest a modification to the ACT 1 Logic Module that would allow the implementation of a three-input NAND using one of your new Logic Modules.
  • c. Can you think of a reason why Actel did not use your modification to its Logic Module design? Hi nt: The modification has to do with routing, and not the logic itself.

7.7 (*Actel architecture, 60 min.) This is a long but relatively straightforward problem that “reverse-engineers” the Actel architecture. If you measured the chip photo on the front of the April 1990 Actel data book, you would find the following:

  1. Die height (scribe to scribe) = 170 mm.
  2. Channel height = 8 mm (there are 7 full-height and 2 half-height channels).
  3. Logic Module height = 5 mm (there are 8 rows of Logic Modules).
  4. Column (Logic Module) width = 4.2 mm.

(The scribe line is an area at the edge of a die where a cut is made by a diamond saw when the dice are separated.) An Actel 1010 die in 2 m m technology is 240 mil high by 360 mil wide (p. 4-17 in the 1990 data book). Assuming these data book dimensions are scribe to scribe, calculate (a)  the Logic Module height, (b)  the channel height, and (c)  the column (Logic Module) width.

Given that there are 25 tracks per horizontal channel, and 13 tracks per column in the vertical direction, calculate (d)  the horizontal channel track spacing and (e) the vertical channel track spacing. (f)  Using the fact that each output stub spans two channels above and below the Logic Module, calculate the height of the output stub.

We can now estimate the capacitance of the Logic Module stubs and interconnect. Assume the interconnect capacitance is 0.2 pFmm –1 . (g)  Calculate the capacitance of an output stub and an input stub. (h)  Calculate the width and thus the capacitance of the horizontal tracks that are from four columns to 44 columns long.

You should not have to make any other assumptions to calculate these figures, but if you do, state them clearly. The figures you have calculated are summarized in Table 7.2 .

7.8 (Xilinx bank shots, 20 min.) Figure 7.11 shows a magic box. Explain how to use a “bank shot” to enter one side of the box, bounce off another, and exit on a third side. What is the delay involved in this maneuver?

FIGURE 7.11  A Xilinx magic box showing one set of connections from connection 1 (Problem 7.8).

 


Chapter start ] [ Previous page ] [ Next page ]

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy