7.7  Summary

The RC product of the parasitic elements of an antifuse and a pass transistor are not too different. However, an SRAM cell is much larger than an antifuse which leads to coarser interconnect architectures for SRAM-based programmable ASICs. The EPROM device lends itself to large wired-logic structures. These differences in programming technology lead to different architectures:

  • The antifuse FPGA architectures are dense and regular.
  • The SRAM architectures contain nested structures of interconnect resources.
  • The complex PLD architectures use long interconnect lines but achieve deterministic routing.

Table 7.4 is a look-up table for Tables 7.5 and 7.6 , which summarize the features of the logic cells used by the various FPGA vendors.

TABLE 7.4  I/O Cell Tables.

Table

Programmable ASIC family

 

Table

Programmable ASIC family

Table 7.5

Actel (ACT 1)

Xilinx (XC3000)

Actel (ACT 2)

Xilinx (XC4000)

Altera MAX (EPM 5000)

Xilinx EPLD (XC7200/7300)

Actel (ACT 3)

QuickLogic (pASIC 1)

Crosspoint (CP20K)

Altera MAX (EPM 7000)

Atmel (AT6000)

Xilinx LCA (XC5200)

 

Table 7.6

Xilinx (XC8100)

Lucent ORCA (2C)

Altera FLEX (8000/10k)

AMD MACH 5

Actel 3200DX

Altera MAX (EPM 9000)

TABLE 7.5  Programmable ASIC interconnect.

 

Actel (ACT 1)

Xilinx (XC3000)

Actel (ACT 2)

Xilinx (XC4000)

Interconnect between logic cells (tracks = trks)

Channeled array with segmented routing, long lines:

25 trks/ch. (horiz.); 13 trks/ch. (vert.);

< 4 antifuses/path

Switch box, PIPs (Programmable Interconnect Points), 3-state internal bus, and long lines

Channeled array with segmented routing, long lines:

36 trks/ch. (horiz.); 15 trks/ch. (vert.);

< 4 antifuses/path

Switch box, PIPs (Programmable Interconnect Points), 3-state internal bus, and long lines

Interconnect delay

Variable

Variable

Variable

Variable

Interconnect inside logic cells

Poly–diffusion antifuse

32-bit SRAM LUT

Poly–diffusion antifuse

32-bit SRAM

LUT

 

 

 

 

 

 

 

 

Altera (MAX 5000)

Xilinx EPLD

QuickLogic (pASIC 1)

Actel (ACT 3)

Interconnect between logic cells

Cross-bar PIA

(Programmable Interconnect Architecture) using EPROM programmable-AND array

UIM (Universal Interconnect Matrix) using EPROM programmable-AND array

Programmable

fully populated

antifuse matrix

Channeled array with segmented routing, long lines: <4 antifuses/path

Interconnect delay

Fixed

Fixed

Variable

Variable

Interconnect inside logic cells

EPROM

EPROM

Metal–metal antifuse

Poly–diffusion antifuse

 

 

 

 

 

 

 

 

Crosspoint (CP20K)

Altera MAX

(MAX 7000)

Atmel (AT6000)

Xilinx LCA (XC5200)

Interconnect between logic cells

Programmable highly

interconnected matrix

Fixed cross-bar PIA (Programmable Interconnect Architecture)

Programmable regular, local, and express bus scheme with line repeaters

Switch box, PIPs (Programmable Interconnect Points), 3-state internal bus, and long lines

Interconnect delay

Variable

Fixed

Variable

Variable

Interconnect inside logic cells

Metal–metal

antifuse

EEPROM

SRAM

16-bit SRAM

LUT

TABLE 7.6  Programmable ASIC interconnect (continued).

 

Xilinx (XC8100)

Lucent ORCA 2C

Altera FLEX 8000/10k

Interconnect between logic cells

Channeled array with

segmented routing, long lines. Programmable fully populated antifuse matrix.

Switch box, SRAM programmable interconnect, 3-state internal bus, and long lines

Row and column FastTrack between LABs

Interconnect delay

Variable

Variable

Fixed with small variation in delay in row FastTrack

Interconnect inside logic cells

Antifuse

SRAM LUTs and MUXs

LAB local interconnect between LEs. 16-bit SRAM LUT in LE.

 

 

 

 

 

AMD MACH 5

Actel 3200DX

Altera MAX 9000

Interconnect between logic cells

EPROM programmable array

Channeled gate array

with segmented routing, long lines

Row and column FastTrack between LABs

Interconnect delay

Fixed

Variable

Fixed

Interconnect inside logic cells

EPROM

Poly–diffusion antifuse

Programmable AND array inside LAB, EEPROM MUXes

The key points covered in this chapter are:

  • The difference between deterministic and nondeterministic interconnect
  • Estimating interconnect delay
  • Elmore’s constant

Next, in Chapter 8, we shall cover the software you need to design with the various FPGA families and explain how FPGAs are programmed.


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