5.5  Summary

Table 5.4 is a look-up table to Tables 5.5 5.9 , which summarize the features of the logic cells used by the various FPGA vendors.

TABLE 5.4  Logic cell tables.

Programmable ASIC family

 

Programmable ASIC family

Table 5.5

Actel (ACT 1)

Xilinx (XC3000)

Actel (ACT 2)

Xilinx (XC4000)

 

Table 5.8

Actel (ACT 3)

Xilinx LCA (XC5200)

Altera FLEX (8000/10k)

Table 5.6

Altera MAX (EPM 5000)

Xilinx EPLD (XC7200/7300)

QuickLogic (pASIC 1)

 

Table 5.9

AMD MACH 5

Actel 3200DX

Altera MAX (EPM 9000)

Table 5.7

Crosspoint (CP20K)

Altera MAX (EPM 7000)

Atmel (AT6000)

 

 

 

TABLE 5.5  Logic cells used by programmable ASICs.

 

Actel ACT 1

Xilinx XC3000

Actel ACT 2

Xilinx XC4000

Basic
logic cell

Logic module (LM)

CLB (Configurable Logic Block)

C-Module (combinatorial-module) and S-Module (sequential module)

CLB (Configurable Logic Block)

Logic cell
contents

Three 2:1MUXes plus OR gate

32-bit LUT, 2 D flip-flops, 9 MUXes

C-Module: 4:1 MUX, 2-input OR, 2-input AND

S-Module: 4-input MUX, 2-input OR, latch or D flip-flop

32-bit LUT, 2 D flip-flops, 10 MUXes, including fast carry logic

E-suffix parts contain dual-port RAM.

Logic path
delay

Fixed

Fixed with ability to bypass FF

Fixed

Fixed with ability to bypass FF

Combinational logic
functions

Most 3-input, many 4-input functions (total 702 macros)

All 5-input functions plus 2 D flip-flops

Most 3- and 4-input functions (total 766 macros)

Two 4-input LUTs plus combiner with ninth input

CLB as 32-bit SRAM (except D-suffix parts)

Flip-flop (FF)

implementation

1 LM required for latch, 2 LMs required for flip-flops

2 D-flip-flops per CLB, latches can be built from pre-FF logic.

1 S-Module per D flip-flop; some FFs require 2 modules.

2 D flip-flops per CLB

Basic logic cells
in each chip

LMs:

 

  A1010: 352   (8R ¥ 44C)

   = 295 + 57 I/O

 

  A1020: 616   (14 R ¥ 44C)

   = 547 + 69 I/O

   64 (XC3020/A/L, XC3120/A)

100 (XC3030/A/L, XC3130/A)

144 (XC3042/A/L, XC3142/A)

224 (XC3064/A/L, XC3164/A)

320 (XC3090/A/L, XC3190/A)

484 (XC3195/A)

A1225:

 451 = 231 S + 220 C

 

A1240:

 684 = 348 S + 336 C

 

A1280:

 1232 = 624 S +  608 C

64 (XC4002A)

100 (XC4003/A/E/H)

144 (XC4004A)

196 (XC4005/A/E/H)

256 (XC4006/E)

324 (XC4008/E)

400 (XC4010/D/E)

576 (XC4013/D/E)

784 (XC4020/E)

1024 (XC4025/E)

TABLE 5.6  Logic cells used by programmable ASICs.

 

Altera MAX 5000

Xilinx XC7200/7300

QuickLogic pASIC 1

Basic
logic cell

16 macrocells in a LAB (Logic Array Block) except EPM5032, which has 32 macrocells in a single LAB

9 macrocells within a FB (Functional Block), fast FBs (FFBs) omit ALU

Logic Cell (LC)

Logic cell
contents

Macrocell: 64–106-wide AND, 3-wide OR array, 1 flip-flop, 2 MUXes, programmable inversion. 32–64 shared logic expander OR terms.

LAB looks like a 32V16 PLD.

Macrocell: 21-wide AND, 16-wide OR array, 1 flip-flop, 1ALU

FB looks like 21V9 PLD.

Four 2-input and two 6-input AND, three 2:1 MUXes and one D flip-flop

Logic path
delay

Fixed (unless using shared logic expanders)

Fixed

Fixed

Combinational
logic functions
per logic cell

Wide input functions with ability to share product terms

Wide input functions with added 2-input ALU

All 3-input functions

Flip-flop (FF)

implementation

1 D flip-flop or latch per macrocell. More can be constructed in arrays.

1 D flip-flop or latch per macrocell

1 D flip-flop per LC. LCs for other flip-flops not specified.

Basic logic cells
in each chip

LABs:

    32 (EPM5032)

    64 (EPM5064)

   128 (EPM5128)

   128 (EPM5130)

   192 (EPM5192)

FBs:

    4 (XC7236A)

    8 (XC7272A)

    2 (XC7318)

    4 (XC7336)

    6 (XC7354)

    8 (XC7372)

   12 (XC73108)

   16 (XC73144)

48 (QL6X8)

96 (QL8X12)

192 (QL12X16)

384 (QL16X24)

TABLE 5.7  Logic cells used by programmable ASICs.

 

Crosspoint CP20K

Altera MAX 7k

Atmel AT6000

Basic
logic cell

Transistor-pair tile (TPT), RAM-logic Tile (RLT)

16 macrocells in a LAB (Logic Array Block)

Cell

Logic cell
contents

TPT: 2 transistors (0.5 gate). RLT: 3 inverters, two 3-input NANDs, 2-input NAND, 2-input AND.

Macrocell: wide AND, 5-wide OR array, 1 flip-flop, 3 MUXes, programmable inversion. 16 shared logic expander OR terms, plus parallel logic expander.

LAB looks like a 36V16 PLD.

Two 5:1 MUXes, two 4:1 MUXes, 3:1 MUX, three 2:1 MUXes, 6 pass gates, four 2-input gates, 1 D flip-flop

Logic path
delay

Variable

Fixed (unless using shared logic expanders)

Variable

Combinational
functions
per logic cell

TPT is smaller than a gate, approx. 2 TPTs = 1 gate.

Wide input functions with ability to share product terms

1-, 2-, and 3-input combinational configurations:

44 logical states and 72 physical states

Flip-flop (FF)

implementation

D flip-flop requires 2 RLTs and 9 TPTs

1 D flip-flop or latch per macrocell. More can be constructed in arrays.

1 D flip-flop per cell

Basic logic cells
in each chip

TPTs:

   1760 (20220)

   15,876 (22000)

 

RLTs:

    440 (20220)

   3969 (22000) 

Macrocells:

    32 (EPM7032/V)

    64 (EPM7064)

    96 (EPM7096)

   128 (EPM70128E)

   160 (EPM70160E)

   192 (EPM70192E)

   256 (EPM70256E)

1024 (AT6002)

1600 (AT6003)

3136 (AT6005)

6400(AT6010)

TABLE 5.8  Logic cells used by programmable ASICs.

 

Actel ACT 3

Xilinx XC5200

Altera FLEX 8000/10k

Basic
logic cell

2 types of Logic

Module: C-Module and

S-Module (similar but not identical to ACT 2)

4 Logic Cells (LC) in a CLB (Configurable Logic Block)

8 Logic Elements (LE) in a Logic Array Block (LAB )

Logic cell contents

(LUT = look-up table)

C-Module: 4:1 MUX, 2-input OR, 2-input AND.

S-Module: 4:1 MUX, 2-input OR, latch or D flip-flop.

LC has 16-bit LUT, 1 flip-flop (or latch), 4 MUXes

16-bit LUT,
1 programmable flip-flop or latch, MUX logic for control, carry logic, cascade logic

Logic path delay

Fixed

Fixed

Fixed with ability to
bypass FF

Combinational
functions
per logic cell

Most 3- and 4-input functions (total 766 macros)

One 4-input LUT per LC may be combined with adjacent LC to form 5-input LUT

4-input LUT may be cascaded with adjacent LE

Flip-flop (FF)

implementation

1 D flip-flop (or latch) per S-Module; some FFs require 2 modules.

1 D flip-flop (or latch) per LC (4 per CLB)

1 D flip-flop (or latch) per LE

Basic logic cells
in each chip

 

A1415: 104 S + 96 C

A1425: 160 S + 150 C

A1440: 288 S + 276 C

A1460: 432 S + 416 C

A14100: 697 S + 680 C

64 CLB (XC5202)

120 CLB (XC5204)

196 CLB (XC5206)

324 CLB (XC5210)

484 CLB (XC5215)

LEs:

    208 (EPF8282/V/A /AV)

    336 (EPF8452/A)

    504 (EPF8636A)

    672 (EPF8820/A)

   1008 (EPF81188/A)

   1296 (EPF81500/A)

 

    576 (EPF10K10)

   1152 (EPF10K20)

   1728 (EPF10K30)

   2304 (EPF10K40)

   2880 (EPF10K50)

   3744 (EPF10K70)

   4992 (EPF10K100)

TABLE 5.9  Logic cells used by programmable ASICs.

 

AMD MACH 5

Actel 3200DX

Altera MAX 9000

Basic
logic cell

4 PAL Blocks in a Segment, 16 macrocells in a PAL Block

Based on ACT 2, plus D-module (decode) and dual-port SRAM

16 macrocells in a LAB (Logic Array Block)

Logic cell
contents

20-bit to 32-bit wide OR array, switching logic, XOR gate, programmable flip-flop

C-Module: 4:1 MUX, 2-input OR, 2-input AND

S-Module: 4-input MUX, 2-input OR, latch or D flip-flop

 

D-module: 7-input AND, 2-input XOR

Macrocell: 114-wide AND, 5-wide OR array, 1 flip-flop, 5 MUXes, programmable inversion. 16 shared logic expander OR terms, plus parallel logic expander.

LAB looks like a 49V16 PLD.

Logic path
delay

Fixed

Fixed

Fixed (unless using expanders)

Combinational functions per logic cell

Wide input functions

Most 3- and 4-input functions (total 766 macros)

Wide input functions with ability to share product terms

Flip-flop (FF)

implementation

1 D flip-flop or latch per macrocell

1 D flip-flop or latch per S-Module; some FFs require 2 modules.

1 D flip-flop or latch per macrocell. More can be constructed in arrays.

Basic logic cells
in each chip

 

128 (M5-128)

192 (M5-192)

256 (M5-256)

320 (M5-320)

384 (M5-384)

512 (M5-512)

A3265DX: 510 S + 475 C + 20 D

A32100DX: 700 S + 662 C + 20 D + 2 kSRAM

A32140D): 954 S + 912 C + 24 D

A32200DX: 1 230 S + 1 184 C + 24 D + 2.5 kSRAM

A32300DX: 1 888 S + 1 833 C + 28 D + 3kSRAM

A32400DX: 2 526 S + 2 466 C + 28 D + 4 kSRAM

Macrocells:

   320 (EPM9320) 4 ¥ 5

   LABs

   400 (EPM9400) 5 ¥ 5

   LABs

   480 (EPM9480) 6 ¥ 5

   LABs

   560 (EPM9560) 7 ¥ 5

   LABs

The key points in this chapter are:

  • The use of multiplexers, look-up tables, and programmable logic arrays
  • The difference between fine-grain and coarse-grain FPGA architectures
  • Worst-case timing design
  • Flip-flop timing
  • Timing models
  • Components of power dissipation in programmable ASICs
  • Deterministic and nondeterministic FPGA architectures

Next, in Chapter 6, we shall examine the I/O cells used by the various programmable ASIC families.


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