When the p -channel transistor in an inverter is charging a capacitance, C , at a frequency, f , the current through the transistor is C (d V /d t ). The power dissipation is thus CV (d V /d t ) for one-half the period of the input, t = 1/(2 f ). The power dissipated in the p -channel transistor is thus
Most of the power dissipation in a CMOS ASIC arises from this source—the switching current. The best way to reduce power is to reduce V DD (because it appears as a squared term in Eq. 15.4 ), and to reduce C , the amount of capacitance we have to switch. A rough estimate is that 20 percent of the nodes switch (or toggle) in a circuit per clock cycle. To determine more accurately the power dissipation due to switching, we need to find out how many nodes toggle during typical circuit operation using a dynamic logic simulator. This requires input vectors that correspond to typical operation, which can be difficult to produce. Using a digital simulator also will not take into account the effect of glitches, which can be significant. Power simulators are usually a hybrid between SPICE transistor-level simulators and digital event-driven simulators [ Najm, 1994].
The short-circuit current or crowbar current can be particularly important for output drivers and large clock buffers. For a CMOS inverter (see Problem 15.17 ) the power dissipation due to the crowbar current is
where we assume the following: We ratio the p -channel and n -channel transistor sizes so that b = ( W/L ) m C ox is the same for both p - and n -channel transistors, the magnitude of the threshold voltages V t n are assumed equal for both transistor types, and t rf is the rise and fall time (assumed equal) of the input signal [ Veendrick, 1984]. For example, consider an output buffer that is capable of sinking 12 mA at an output voltage of 0.5 V. From Eq. 2.9 we can derive the transistor gain factor that we need as follows:
As a general rule, if we adjust the transistor sizes so that the rise times and fall times through a chain of logic are approximately equal (as they should be), the short-circuit current is typically less than 20 percent of the switching current.
For the example output buffer, we can make a rough estimate of the output-node switching time by assuming the buffer output drive current is constant at 12 mA. This current will cause the voltage on the output load capacitance to change between 3.3 V and 0 V at a constant slew rate d V /d t for a time
This is close to the input rise time of 2 ns. So our estimate of the short-circuit current being less than 20 percent of the switching current assuming equal input rise time and output rise time is valid in this case.
Despite the claim made in Section 2.1, a CMOS transistor is never completely off . For example, a typical specification for a 0.5 m m process for the subthreshold current (per micron of gate width for V GS = 0 V) is less than 5 pA m m –1 , but not zero. With 10 million transistors on a large chip and with each transistor 10 m m wide, we will have a total subthreshold current of 0.1 mA; high, but reasonable. The problem is that the subthreshold current does not scale with process technology.
For example, at a junction temperature, T = 125 °C ( ª 400 K) and assuming n ª 1.5, S = 120 mV/decade ( q = 1.6 ¥ 10 –19 Fm –1 , k = 1.38 ¥ 10 –23 JK –1 ), which does not scale. The constant value of S = 120 mV/decade means it takes 120 mV to reduce the subthreshold current by a factor of 10 in any process. If we reduce the threshold voltages to 0.36 V in a deep-submicron process, for example, this means at V GS = 0 V we can only reduce I DS to 0.001 times its value at V GS = V t . This problem can lead to large static currents.
Transistor leakage is caused by the fact that a reverse-biased diode conducts a very small leakage current. The sources and drains of every transistor, as well as the junctions between the wells and substrate, form parasitic diodes. The parasitic-diode leakage currents are strongly dependent on the type and quality of the process as well as temperature. The parasitic diodes have two components in parallel: an area diode and a perimeter diode. The ideal parasitic diode currents are given by the following equation:
Table 15.6 shows specified maximum leakage currents of junction parasitic diodes as well as the leakage currents of the field transistors (the parasitic MOS transistors formed when poly crosses over the thick oxide, or field oxide) in a typical 0.5 m m process.
or approximately 3 m A. This is the same order of magnitude (a few microamperes) as the quiescent leakage current, I DDQ , that we expect to measure when we test an ASIC with power applied, but with no signal activity. A measurement of more current than this in a nonactive CMOS ASIC indicates a problem with the chip manufacture or the design. We use this measurement to test an ASIC using an IDDQ test.
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