13.10  Transistor-Level Simulation

Sometimes we need to simulate a logic circuit with more accuracy than provided by switch-level simulation. In this case we turn to simulators that can solve circuit equations exactly, given models for the nonlinear transistors, and predict the analog behavior of the node voltages and currents in continuous time. This type of transistor-level simulation or circuit-level simulation is costly in computer time. It is impossible to simulate more than a few hundred logic cells using a circuit-level simulator. Virtually all circuit-level simulators used for ASIC design are commercial versions of the SPICE (or Spice , Simulation Program with Integrated Circuit Emphasis ) developed at UC Berkeley.

FIGURE 13.2  Output buffer (OB.IN) schematic (created using Capilano’s DesignWorks)

 

13.10.1 A PSpice Example

Figure 13.2 shows the schematic for the output section of a CMOS I/O buffer driving a 10 pF output capacitor representing an off-chip load. The PSpice input file that follows is called a deck (from the days of punched cards):

OB September 5, 1996 17:27

.TRAN/OP 1ns 20ns

.PROBE

cl output Ground 10pF

VIN input Ground PWL(0us 5V 10ns 5V 12ns 0V 20ns 0V)

VGround 0 Ground DC 0V

Vdd +5V 0 DC 5V

m1 output input Ground Ground NMOS W=100u L=2u

m2 output input +5V +5V PMOS W=200u L=2u

.model nmos nmos level=2 vto=0.78 tox=400e-10 nsub=8.0e15 xj=-0.15e-6

+ ld=0.20e-6 uo=650 ucrit=0.62e5 uexp=0.125 vmax=5.1e4 neff=4.0

+ delta=1.4 rsh=37 cgso=2.95e-10 cgdo=2.95e-10 cj=195e-6 cjsw=500e-12

+ mj=0.76 mjsw=0.30 pb=0.80

.model pmos pmos level=2 vto=-0.8 tox=400e-10 nsub=6.0e15 xj=-0.05e-6

+ ld=0.20e-6 uo=255 ucrit=0.86e5 uexp=0.29 vmax=3.0e4 neff=2.65

+ delta=1 rsh=125 cgso=2.65e-10 cgdo=2.65e-10 cj=250e-6 cjsw=350e-12

+ mj=0.535 mjsw=0.34 pb=0.80

.end

Figure 13.3 shows the input and output waveforms as well as the current flowing in the devices.We can quickly check our circuit simulation results as follows. The total charge transferred to the 10 pF load capacitor as it charges from 0 V to 5 V is 50 pC (equal to 5 V ¥ 10 pF). This total charge should be very nearly equal to the integral of the drain current of the pull-up ( p -channel) transistor I L ( m2 ). We can get a quick estimate of the integral of the current by approximating the area under the waveform for id(m2) in Figure 13.3 as a triangle—half the base (about 12 ns) multiplied by the height (about 8 mA), so that

 

22 ns

 

 

 

 

 

Ú

 

I L (m2) d t

=

0.5 (8 mA) (12 ns)

 

(13.28)

 

10 ns

 

 

 

 

 

 

 

 

ª

50 pC

 

 

 

 

 

ª

5 (10 pF)

 

 

Notice that the two estimates for the transferred charge are equal.

 

 

FIGURE 13.3  Output Buffer (OB.IN). (Top) The input and output voltage waveforms. (Bottom) The current flowing in the drains of the output devices.

Next, we can check the time derivative of the pull-up current. (We can also do this by using the Probe program and requesting a plot of did(m2) ; the symbol dn represents the time derivative of quantity n for Probe. The symbol id(m2) requests Probe to plot the drain current of m2 .) The maximum derivative should be roughly equal to the maximum change of the drain current ( D I L ( m 2) = 8 mA) divided by the time taken for that change (about D t = 2 ns from Figure 13.3 ) or

| D I L (m2) |

 

8 mA

 

 

 

–––––––––

=

––––––

=

4 ¥ 10 6 As –1

(13.29)

D t

 

2 ns

 

 

 

The large time derivative of the device current, here 4 MAs –1 , causes problems in high-speed CMOS I/O. This sharp change in current must flow in the supply leads to the chip, and through the inductance associated with the bonding wires to the chip which may be of the order of 10 nanohenrys. An electromotive force (emf ), V P , will be generated in the inductance as follows,

 

 

 

d I

 

 

V P

=

L

–––

 

(13.30)

 

 

 

d t

 

 

 

 

 

 

 

 

 

=

–10 nH (4 ¥ 10 6 ) As –1

 

 

 

 

 

 

 

 

=

–40 mV

 

The result is a glitch in the power supply voltage during the buffer output transient. This is known as supply bounce or ground bounce . To limit the amount of bounce we may do one of two things:

  1. Limit the power supply lead inductance (minimize L)
  2. Reduce the current pulse (minimize dI/dt)

We can work on the first solution by careful design of the packages and by using parallel bonding wires (inductors add in series, reduce in parallel).

13.10.2 SPICE Models

Table 13.14 shows the SPICE parameters for the typical 0.5 m m CMOS process (0.6 m m drawn gate length), G5, that we used in Section 2.1 . These LEVEL = 3 parameters may be used with Spice3, PSpice, and HSPICE (see also Table 2.1 and Figure 2.4 ).

TABLE 13.14  SPICE transistor model parameters ( LEVEL = 3 ).

SPICE
parameter 1

n-channel

value

p-channel

value

(if different)

Units 2

 

Explanation

CGBO

4.0E-10

3.8E-10

Fm –1

 

Gate–bulk overlap capacitance (CGBoh, not CGBzero)

CGDO

3.0E-10

2.4E-10

Fm –1

 

Gate–drain overlap capacitance (CGDoh, not CGDzero)

CGSO

3.0E-10

2.4E-10

Fm –1

 

Gate–source overlap capacitance (CGSoh, not CGSzero)

CJ

5.6E-4

9.3E-4

Fm –2

 

Junction area capacitance

CJSW

5E-11

2.9E-10

Fm –1

 

Junction sidewall capacitance

DELTA

0.7

0.29

m

 

Narrow-width factor for adjusting threshold voltage

ETA

3.7E-2

2.45E-2

1

 

Static-feedback factor for adjusting threshold voltage

GAMMA

0.6

0.47

V 0.5

 

Body-effect factor

KAPPA

2.9E-2

8

V –1

 

Saturation-field factor (channel-length modulation)

KP

2E-4

4.9E-5

AV –2

 

Intrinsic transconductance ( m Cox , not 0.5 m Cox )

LD

5E-8

3.5E-8

m

 

Lateral diffusion into channel

LEVEL

3

 

none

 

Empirical model

MJ

0.56

0.47

1

 

Junction area exponent

MJSW

0.52

0.50

1

 

Junction sidewall exponent

NFS

6E11

6.5E11

cm –2 V –1

 

Fast surface-state density

NSUB

1.4E17

8.5E16

cm –3

 

Bulk surface doping

PB

1

1

V

 

Junction area contact potential

PHI

0.7

 

V

 

Surface inversion potential

RSH

2

 

W / square

 

Sheet resistance of source and drain

THETA

0.27

0.29

V –1

 

Mobility-degradation factor

TOX

1E-8

 

m

 

Gate-oxide thickness

TPG

1

-1

none

 

Type of polysilicon gate

U0

550

135

cm 2 V –1 s –1

 

Low-field bulk carrier mobility (Uzero, not Uoh)

XJ

0.2E-6

 

m

 

Junction depth

VMAX

2E5

2.5E5

ms –1

 

Saturated carrier velocity

VTO

0.65

-0.92

V

 

Zero-bias threshold voltage (VTzero, not VToh)

There are several levels of the SPICE MOSFET models, the following is a simplified overview (a huge number of confusing variations, fixes, and options have been added to these models—see Meta Software’s HSPICE User’s Manual, Vol. II, for a comprehensive description [ 1996]):

  1. LEVEL = 1 ( Schichman–Hodges model ) uses the simple square-law I DS V DS relation we derived in Section 2.1 (Eqs. 2.9 and 2.12).
  2. LEVEL = 2 ( Grove–Frohman model ) uses the 3/2 power equations that result if we include the variation of threshold voltage across the channel.
  3. LEVEL = 3 ( empirical model ) uses empirical equations.
  4. The UCB BSIM1 model (~1984, PSpice LEVEL = 4 , HSPICE LEVEL = 13 ) focuses on modeling observed device data rather than on device physics. A commercial derivative (HSPICE LEVEL = 28 ) is widely used by ASIC vendors.
  5. The UCB BSIM2 model (~1991, the commercial derivative is HSPICE LEVEL = 39 ) improves modeling of subthreshold conduction.
  6. The UCB BSIM3 model (~1995, the commercial derivative is HSPICE LEVEL = 49 ) corrects potential nonphysical behavior of earlier models.
  7. TABLE 13.15  PSpice parameters for process G5 (PSpice LEVEL = 4 ). 3

    .MODEL NM1 NMOS LEVEL=4

    + VFB=-0.7, LVFB=-4E-2, WVFB=5E-2

    + PHI=0.84, LPHI=0, WPHI=0

    + K1=0.78, LK1=-8E-4, WK1=-5E-2

    + K2=2.7E-2, LK2=5E-2, WK2=-3E-2

    + ETA=-2E-3, LETA=2E-02, WETA=-5E-3

    + MUZ=600, DL=0.2, DW=0.5

    + U0=0.33, LU0=0.1, WU0=-0.1

    + U1=3.3E-2, LU1=3E-2, WU1=-1E-2

    + X2MZ=9.7, LX2MZ=-6, WX2MZ=7

    + X2E=4.4E-4, LX2E=-3E-3, WX2E=9E-4

    + X3E=-5E-5, LX3E=-2E-3, WX3E=-1E-3

    + X2U0=-1E-2, LX2U0=-1E-3, WX2U0=5E-3

    + X2U1=-1E-3, LX2U1=1E-3, WX2U1=-7E-4

    + MUS=700, LMUS=-50, WMUS=7

    + X2MS=-6E-2, LX2MS=1, WX2MS=4

    + X3MS=9, LX3MS=2, WX3MS=-6

    + X3U1=9E-3, LX3U1=2E-4, WX3U1=-5E-3

    + TOX=1E-2, TEMP=25, VDD=5

    + CGDO=3E-10, CGSO=3E-10, CGBO=4E-10

    + XPART=1

    + N0=1, LN0=0, WN0=0

    + NB=0, LNB=0, WNB=0

    + ND=0, LND=0, WND=0

    * n+ diffusion

    + RSH=2.1, CJ=3.5E-4, CJSW=2.9E-10

    + JS=1E-8, PB=0.8, PBSW=0.8

    + MJ=0.44, MJSW=0.26, WDF=0

    *, DS=0

    .MODEL PM1 PMOS LEVEL=4

    + VFB=-0.2, LVFB=4E-2, WVFB=-0.1

    + PHI=0.83, LPHI=0, WPHI=0

    + K1=0.35, LK1=-7E-02, WK1=0.2

    + K2=-4.5E-2, LK2=9E-3, WK2=4E-2

    + ETA=-1E-2, LETA=2E-2, WETA=-4E-4

    + MUZ=140, DL=0.2, DW=0.5

    + U0=0.2, LU0=6E-2, WU0=-6E-2

    + U1=1E-2, LU1=1E-2, WU1=7E-4

    + X2MZ=7, LX2MZ=-2, WX2MZ=1

    + X2E= 5E-5, LX2E=-1E-3, WX2E=-2E-4

    + X3E=8E-4, LX3E=-2E-4, WX3E=-1E-3

    + X2U0=9E-3, LX2U0=-2E-3, WX2U0=2E-3

    + X2U1=6E-4, LX2U1=5E-4, WX2U1=3E-4

    + MUS=150, LMUS=10, WMUS=4

    + X2MS=6, LX2MS=-0.7, WX2MS=2

    + X3MS=-1E-2, LX3MS=2, WX3MS=1

    + X3U1=-1E-3, LX3U1=-5E-4, WX3U1=1E-3

    + TOX=1E-2, TEMP=25, VDD=5

    + CGDO=2.4E-10, CGSO=2.4E-10, CGBO=3.8E-10

    + XPART=1

    + N0=1, LN0=0, WN0=0

    + NB=0, LNB=0, WNB=0

    + ND=0, LND=0, WND=0

    * p+ diffusion

    + RSH=2, CJ=9.5E-4, CJSW=2.5E-10

    + JS=1E-8, PB=0.85, PBSW=0.85

    + MJ=0.44, MJSW=0.24, WDF=0

    *, DS=0

Table 13.15 shows the BSIM1 parameters (in the PSpice LEVEL = 4 format) for the G5 process. The Berkeley short-channel IGFET model ( BSIM ) family models capacitance in terms of charge. In Sections 2.1 and 3.2 we treated the gate–drain capacitance, C GD , for example, as if it were a reciprocal capacitance , and could be written assuming there was charge associated with the gate, Q G , and the drain, Q D , as follows:

 

 

-∂ Q G

 

 

 

-∂ Q D

 

 

C GD

=

––––

=

C DG

=

––––

 

(13.31)

 

 

V D

 

 

 

V G

 

 

Equation  13.31 (the Meyer model ) would be true if the gate and drain formed a parallel plate capacitor and Q G = – Q D , but they do not. In general, Q G ≠ – Q D and Eq.  13.31 is not true. In an MOS transistor we have four regions of charge: Q G (gate), Q D (channel charge associated with the drain), Q S (channel charge associated with the drain), and Q B (charge in the bulk depletion region). These charges are not independent, since

Q G + Q D + Q S + Q B

=

0

 

(13.32)

We can form a 4 ¥ 4 matrix, M , whose entries are ∂ Q i /∂ V j , where V j = V G , V S , V D , and V B . Then C ii = M ii are the terminal capacitances; and C ij = – M ij , where i j , is a transcapacitance . Equation  13.32 forces the sum of each column of M to be zero. Since the charges depend on voltage differences, there are only three independent voltages ( V GB , V DB , and V SB , for example) and each row of M must sum to zero. Thus, we have nine (= 16 – 7) independent entries in the matrix M . In general, C ij is not necessarily equal to C ji . For example, using PSpice and a LEVEL = 4 BSIM model, there are nine independent partial derivatives, printed as follows:

Derivatives of gate (dQg/dVxy) and bulk (dQb/dVxy) charges

DQGDVGB 1.04E-14

DQGDVDB -1.99E-15

DQGDVSB -7.33E-15

DQDDVGB -1.99E-15

DQDDVDB 1.99E-15

DQDDVSB 0.00E+00

DQBDVGB -7.51E-16

DQBDVDB 0.00E+00

DQBDVSB -2.72E-15

From these derivatives we may compute six nonreciprocal capacitances :

C GB

=

Q G /∂ V GB + ∂ Q G /∂ V DB + ∂ Q G /∂ V SB

 

(13.33)

C BG

=

–∂ Q B /∂ V GB

 

 

C GS

=

–∂ Q G /∂ V SB

 

 

C SG

=

Q G /∂ V GB + ∂ Q B /∂ V GB + ∂ Q D /∂ V GB

 

 

C GD

=

–∂ Q G /∂ V DB

 

 

C DG

=

–∂ Q D /∂ V GB

 

 

and three terminal capacitances:

C GG

=

Q G /∂ V GB

 

(13.34)

C DD

=

Q D /∂ V DB

 

 

C SS

=

–(∂ Q G /∂ V SB + ∂ Q B /∂ V SB + ∂ Q D /∂ V SB )

 

 

Nonreciprocal transistor capacitances cast a cloud over our analysis of gate capacitance in Section 3.2, but the error we made in neglecting this effect is small compared to the approximations we made in the sections that followed. Even though we now find the theoretical analysis was simplified, the conclusions in our treatment of logical effort and delay modeling are still sound. Sections 7.3 and 9.2 in the book on transistor modeling by Tsividis [ 1987] describe nonreciprocal capacitance in detail. Pages 15-42 to 15-44 in Vol. II of Meta Software’s HSPICE User Manual [ 1996] also gives an explanation of transcapacitance.


1. Meta Software’s HSPICE User’s Manual [ 1996], p. 15-36 and pp.16-13 to 16-15, explains these parameters.

2. Note that m or M both represent milli or 10 –3 in SPICE, not mega or 10 6 ( u or U = micro or 10 –6 and so on).

3. PSpice LEVEL = 4 is almost exactly equivalent to the UCB BSIM1 model, and closely equivalent to the HSPICE LEVEL = 13 model (see Table 14-1 and pp. 16–86 to 16-89 in Meta Software’s HSPICE User’s Manual [ 1996].


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