11.11   Altering Parameters


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11.11   Altering Parameters

Here is an example of a module that uses a parameter [Verilog LRM3.10, 12.2]:

module Vector_And(Z, A, B);
  parameter CARDINALITY = 1;
  input [CARDINALITY-1:0] A, B;
  output [CARDINALITY-1:0] Z;
  wire [CARDINALITY-1:0] Z = A & B;
endmodule

We can override this parameter when we instantiate the module as follows:

module Four_And_Gates(OutBus, InBusA, InBusB);
  input [3:0] InBusA, InBusB; output [3:0] OutBus;
  Vector_And #(4) My_AND(OutBus, InBusA, InBusB); // 4 AND gates
endmodule

The parameters of a module have local scope, but we may override them using a defparam statement and a hierarchical name, as in the following example:

module And_Gates(OutBus, InBusA, InBusB);
  parameter WIDTH = 1;
  input [WIDTH-1:0] InBusA, InBusB; output [WIDTH-1:0] OutBus;
  Vector_And #(WIDTH) My_And(OutBus, InBusA, InBusB);
endmodule 
module Super_Size; defparam And_Gates.WIDTH = 4; endmodule


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