10.15  Configurations and Specifications

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10.15  Configurations and Specifications

The difference between, the interaction, and the use of component/configuration declarations and specifications is probably the most confusing aspect of VHDL. Fortunately this aspect of VHDL is not normally important for ASIC design. The syntax of component/configuration declarations and specifications is shown in Table 10.19.

TABLE 10.19    VHDL binding.

configuration
declaration 1
[VHDL LRM1.3]
configuration identifier of entity_name is
  {use_clause|attribute_specification|group_declaration}
  block_configuration
end [configuration] [configuration_identifier];
block
configuration
[VHDL LRM1.3.1]
for architecture_name
  |block_statement_label
  |generate_statement_label [(index_specification)]
{use selected_name {, selected_name};}
{block_configuration|component_configuration}
end for ;
configuration
specification 1
[VHDL LRM5.2]
for
  instantiation_label{,instantiation_label}:component_name
  |others:component_name
  |all:component_name
[use
  entity entity_name [(architecture_identifier)]
  |configuration configuration_name
  |open]
[generic map (generic_association_list)]
[port map (port_association_list)];
component
declaration 1
[VHDL LRM4.5]
component identifier [is]
  [generic (local_generic_interface_list);]
  [port (local_port_interface_list);]
end component [component_identifier];
component
configuration 1
[VHDL LRM1.3.2]
for
instantiation_label {, instantiation_label}:component_name
|others:component_name
|all:component_name
[[use
   entity entity_name [(architecture_identifier)]
  |configuration configuration_name
  |open]
    [generic map (generic_association_list)]
    [port map (port_association_list)];]
[block_configuration]
end for;

 

  • A configuration declaration defines a configuration--it is a library unit and is one of the basic units of VHDL code.
  • A block configuration defines the configuration of a block statement or a design entity. A block configuration appears inside a configuration declaration, a component configuration, or nested in another block configuration.
  • A configuration specification may appear in the declarative region of a generate statement, block statement, or architecture body.
  • A component declaration may appear in the declarative region of a generate statement, block statement, architecture body, or package.
  • A component configuration defines the configuration of a component and appears in a block configuration.

Table 10.20 shows a simple example (identical in structure to the example of Section 10.5) that illustrates the use of each of the preceding constructs.

TABLE 10.20    VHDL binding examples.

 
entity AD2 is port (A1, A2: in BIT; Y: out BIT); end;
architecture B of AD2 is begin Y <= A1 and A2; end;
entity XR2 is port (X1, X2: in BIT; Y: out BIT); end;
architecture B of XR2 is begin Y <= X1 xor X2; end;
 
 
component
declaration
 configuration
 specification
 
entity Half_Adder is port (X, Y: BIT; Sum, Cout: out BIT); end;
architecture Netlist of Half_Adder is use work.all;
component MX port (A, B: BIT; Z :out BIT);end component; 
component MA port (A, B: BIT; Z :out BIT);end component; 
for G1:MX use entity XR2(B) port map(X1 => A,X2 => B,Y => Z);
begin
	G1:MX port map(X, Y, Sum); G2:MA port map(X, Y, Cout); 
end;
configuration
declaration
 block
 configuration
  component
  configuration
 
configuration C1 of Half_Adder is
use work.all;
	for Netlist
		for G2:MA 
			use entity AD2(B) port map(A1 => A,A2 => B,Y => Z);
		end for;
	end for;
end;

1. Underline means "new to VHDL-93".


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