3.2 (Inversion layer depth, 15 min.) In the absence of surface charge, Gauss’s law demands continuity of the electric displacement vector, D = e E , at the silicon surface, so that e ox E ox = e Si E Si , where e ox = 3.9, e Si = 11.7.
3.3 (Depletion layer depth, 15 min.) The depth of the depletion region under the gate is given by x d = ÷[ (2 e Si f s )/(qN A )], where f s = 2V T ln(N A /n i ) is the surface potential at strong inversion. Calculate f s and x d assuming: e Si =1.0359 ¥ 10 –10 Fm –1 , the substrate doping, N A = 1.4 ¥ 10 17 cm –3 , the intrinsic carrier concentration n i = 1.45 ¥ 10 10 cm –3 (at room temperature), and the thermal voltage V T = kT/q = 25.9 mV.
3.4 (Logical effort, 45 min.) Calculate the logical effort at each input of an AOI122 cell. Find an expression that allows you to calculate the logical effort for each input of an AOI nnnn cell for n = 1, 2, 3.
3.5 (Gate-array macro design, 120 min.) Draw a 1X drive, two-input NAND cell using the gate-array base cells shown in Figures 3.14 (a)– 3.16 (lay a piece of thin paper over the figures and draw the contacts and metal personalization only). Label the inputs and outputs. Lay out a 1X drive, four-input NAND cell using the same base array cells. Now lay out a 2X drive, four-input NAND cell (think about this one). Make sure that you size your transistors properly to balance rise times and fall times.
3.6 (Flip-flop library, 20 min.) Suppose we wish to build a library of flip-flops. We want to have flops with: positive-edge and negative-edge triggering: clear, preset (either, both, or neither); synchronous or asynchronous reset and preset controls if present (but not mixed on the same flip-flop); all flip-flops with or without scan as an option; flip-flops with Q and Qbar (either or both). How many flip-flops is that? (***) How would you attempt to prioritize which flip-flops to include in a library?
3.7 (AOI and OAI cell ratios, 30 min.) In Figure 2.13(c) we adjusted the sizes of the transistors assuming that there was only one path through the n -channel and p -channel stacks. Suppose that p -channel transistors A, B, C, and D are all on and p -channel transistor E turns on. What is the equivalent resistance of the p -channel stack in this case?
3.8 (**Eight-input AND, 60 min.) This question is an example in the paper by Sutherland and Sproull  on logical effort. Figure 3.24 shows three different ways to design an eight-input AND cell, using NAND and NOR cells.
3.9 (Special logic cells, 30 min.) Many ASIC cell libraries contain “special” logic cells. For example the Compass libraries contain a two-input NAND cell with an inverted input, FN01 = (A + B'). This saves routing area, is faster than using two separate cells, and is useful because the combination of a two-input NAND gate with one inverted input is heavily used by synthesis tools. Other “special” cells include:
3.10 (Euler paths, 60 min.) There are several ways to arrange the stacks in the AOI211 cell shown in Figure 3.25 . For example, the n -channel transistor A can be below B without altering the function. Which arrangement would you predict gives a faster delay from A to Z and why? The p -channel transistors A and B can be above or below transistors C and D. How many distinct ways of arranging the transistors are there for this cell? What effect do the different arrangements have on layout? What effects do these different arrangements have on the cell performance?
3.12 (**Logical efficiency, 60 min.) Extending Problem 3.11 , let us compare an AOI33 with an OAI33 cell. (a) Calculate the logical effort and (b) logical areas for these cells.
(c) Calculate the path delay, D , as a function of path electrical effort, H , for both of these implementations ignoring parasitic and nonideal delays. (d) Use Eq. 3.42 to calculate the optimum path delay for these cells. (e) Compare and explain the differences between your answers to parts d and e for H = 1, 2, 4, and 8.
3.13 (EXOR cells and logical effort, 60 min.) Show how to implement a two-input EXOR cell using an AOI22 and two inverters. Using logical effort, compare this with an implementation using an AOI21 cell and a NOR cell.
3.14 (***XNOR cells, 60 min.) Table 3.3 shows the implementation of XNOR cells in a standard-cell library. Analyze this data using the concept of logical effort.
The branching effort is the ratio of the on-path plus off-path capacitance to the on-path capacitance. The path effort F becomes the product of the path electrical effort, path branching effort, and path logical effort:
3.16 (*Circuits from layout, 120 min.) Figure 3.26 shows a D flip-flop with clear from a 1.0 m m standard-cell library. Figure 3.27 shows two layout views of this D flip-flop. Construct the circuit diagram for this flip-flop, labeling the nodes and transistors as shown. Include the transistor sizes—use estimates for transistors with 45° gates—you only need W/L values, you can assume the gate lengths are all L = 2 l , equal to the minimum feature size. Label the inputs and outputs to the cell and identify their functions.
3.17 (Flip-flop circuits, 30 min.) Draw the circuit schematic for a positive-edge–triggered D flip-flop with active-high set and reset (base your schematic on Figure 2.18a, a negative-edge–triggered D flip-flop). Describe the problem when both SET and RESET are high.
If we want an active-high set or reset we can: (1) use an inverter on the set or reset signal or (2) we can substitute NOR cells. Since NOR cells are slower than NAND cells, which we do depends on whether we want to optimize for speed or area.
Thus, the largest flip-flop would be one with both Q and QN outputs, active high set and reset—requiring four TX gates, three inverters (four of the seven we normally need are replaced with NAND cells), four NAND cells, and two inverters to invert the set and reset, making a total of 34 transistors, or 8.5 gates.
3.21 (**Optimum logic, 60 min.) Suppose we have a fixed logic path of length n 1 . We want to know how many (if any) buffer stages we should add at the output of this path to optimize the total path delay given the output load capacitance.
3.22 (XOR and XNOR cells, 60 min.) Table 3.4 shows the implementations of two- and three-input XOR cells in an ASIC standard-cell library (D1 are the 1X drive cells, and D2 are the 2X drive versions). Can you explain the choices for the two-input XOR cell and complete the table for the three-input XOR cell?
3.23 (Library density, 10 min.) Derive an upper limit on cell density as follows: Assume a chip consists only of two-input NAND cells with no routing channels between rows (often achievable in a 3LM process with over-the-cell routing).