12.10  The Engine Controller

This section returns to the example from Section 10.16, “An Engine Controller.” This ASIC gathers sampled temperature measurements from sensors, converts the temperature values from Fahrenheit to Centigrade, averages them, and stores them in a FIFO before passing the values to a microprocessor on a three-state bus. We receive the following message from the logic synthesizer when we use the FIFO-controller code shown in Table 10.25:

Warning: Made latches to store values on: net d(4), d(5), d(6), d(7), d(8), d(9), d(10), d(11), in module fifo_control

This message often indicates that we forgot to initialize a variable.

Here is the part of the code from Table 10.25 that assigns to the vector D (the error message for d is in lowercase—remember VHDL is case insensitive):

case sel is

when "01" => D <= D_1 after TPD; r1 <= '1' after TPD;

when "10" => D <= D_2 after TPD; r2 <= '1' after TPD;

when "00" => D(3) <= f1 after TPD; D(2) <= f2 after TPD;

D(1) <= e1 after TPD; D(0) <= e2 after TPD;

when others => D <= "ZZZZZZZZZZZZ" after TPD;

end case ;

When sel = "00" , there is no assignment to D(4) through D(11) . This did not matter in the simulation, but to reproduce the exact behavior of the HDL code the logic synthesizer generates latches to remember the values of D(4) through D(11) .

This problem may be corrected by replacing the "00" choice with the following:

when "00" => D(3) <= f1 after TPD; D(2) <= f2 after TPD;

D(1) <= e1 after TPD; D(0) <= e2 after TPD;

D(11 downto 4) <= "ZZZZZZZZ" after TPD;

The synthesizer recognizes the assignment of the high-impedance logic value 'Z' to a signal as an indication to implement a three-state buffer. However, there are two kinds of three-state buffers: core logic three-state buffers and three-state I/O cells. We want a three-state I/O cell containing a bonding pad and not a three-state buffer located in the core logic. If we synthesize the code in Table 10.25, we get a three-state buffer in the core. Table 12.9 shows the modified code that will synthesize to three-state I/O cells. The signal OE_b drives the output enable (active-low) of the three-state buffers. Table 12.10 shows the top-level code including all the I/O cells.

TABLE 12.9  A modified version of the FIFO controller to drive three-state I/O cells.

library IEEE; use IEEE.STD_LOGIC_1164. all ; use IEEE.NUMERIC_STD. all ;

entity fifo_control is generic TPD:TIME := 1 ns;

port (D_1, D_2: in UNSIGNED(11 downto 0);

sel : in UNSIGNED(1 downto 0) ;

read , f1, f2, e1, e2 : in STD_LOGIC;

r1, r2, w12: out STD_LOGIC; D: out UNSIGNED(11 downto 0);

OE: out STD_LOGIC ) ;

end ;

architecture rtl of fifo_control is

begin process (read, sel, D_1, D_2, f1, f2, e1, e2)

begin

r1 <= '0' after TPD; r2 <= '0' after TPD; OE_b <= '0' after TPD;

if (read = '1') then

w12 <= '0' after TPD;

case sel is

when "01" => D <= D_1 after TPD; r1 <= '1' after TPD;

when "10" => D <= D_2 after TPD; r2 <= '1' after TPD;

when "00" => D(3) <= f1 after TPD; D(2) <= f2 after TPD;

D(1) <= e1 after TPD; D(0) <= e2 after TPD;

D(11 downto 4) <= "00000000" after TPD;

when others => OE_b <= '1' after TPD;

end case ;

elsif (read = '0') then

OE_b <= '0' after TPD; w12 <= '1' after TPD;

else OE_b <= '0' after TPD;

end if ;

end process ;

end rtl;

TABLE 12.10  The top-level VHDL code for the engine controller ASIC.

library COMPASS_LIB, IEEE ;

use IEEE.STD. all ; use IEEE.NUMERIC_STD. all ;

use COMPASS_LIB.STDCOMP. all ; use COMPASS_LIB.COMPASS. all ;

 

entity t_control_ASIC is port (

PadTri : out STD_LOGIC_VECTOR (11 downto 0) ;

PadClk, PadInreset, PadInreadv : in STD_LOGIC_VECTOR ( 0 downto 0) ;

PadInp1, PadInp2 : in STD_LOGIC_VECTOR (11 downto 0) ;

PadInSens : in STD_LOGIC_VECTOR ( 1 downto 0) ) ;

end t_control_ASIC ;

 

architecture structure of t_control_ASIC is

for all : asPadIn use entity COMPASS_LIB.aspadIn(aspadIn) ;

for all : asPadClk use entity COMPASS_LIB.aspadClk(aspadClk);

for all : asPadTri use entity COMPASS_LIB.aspadTri(aspadTri) ;

for all : asPadVdd use entity COMPASS_LIB.aspadVdd(aspadVdd) ;

for all : asPadVss use entity COMPASS_LIB.aspadVss(aspadVss) ;

component pc3c01 port ( cclk : in STD_LOGIC; cp : out STD_LOGIC ); end component ;

component t_control port(T_in1, T_in2 : in UNSIGNED(11 downto 0);

SENSOR: in UNSIGNED( 1 downto 0) ; clk, rd, rst : in STD_LOGIC;

D : out UNSIGNED(11 downto 0); oe_b : out STD_LOGIC ); end component ;

signal T_in1_sv, T_in2_sv : STD_LOGIC_VECTOR(11 downto 0) ;

signal T_in1_un, T_in2_un : UNSIGNED(11 downto 0) ;

signal sensor_sv : STD_LOGIC_VECTOR(1 downto 0) ;

signal sensor_un : UNSIGNED(1 downto 0) ;

signal clk_sv, rd_fifo_sv, reset_sv : STD_LOGIC_VECTOR (0 downto 0) ;

signal clk_core, oe_b : STD_LOGIC ;

signal D_un : UNSIGNED(11 downto 0) ; signal D_sv : STD_LOGIC_VECTOR(11 downto 0) ;

begin --compass dontTouch u* -- synopsys dont_touch etc.

u1 : asPadIn generic map (12,"2:13") port map (t_in1_sv,PadInp1) ;

u2 : asPadIn generic map (12,"14:25") port map (t_in2_sv,PadInp2) ;

u3 : asPadIn generic map (2,"26:27") port map (sensor_sv, PadInSens ) ;

u4 : asPadIn generic map (1,"29") port map (rd_fifo_sv, PadInReadv ) ;

u5 : asPadIn generic map (1,"30") port map (reset_sv, PadInreset ) ;

u6 : asPadIn generic map (1,"32") port map (clk_sv, PadClk) ;

u7 : pc3c01 port map (clk_sv(0), clk_core) ;

u8 : asPadTri generic map (12,"35:38,41:44,47:50") port map (PadTri,D_sv,oe_b);

u9 : asPadVdd generic map ("1,31,34,40,45,52") port map (Vdd) ;

u10: asPadVss generic map ("28,33,39,46,51,53") port map (Vss) ;

T_in1_un <= UNSIGNED(T_in1_sv) ; T_in2_un <= UNSIGNED(T_in2_sv) ;

sensor_un <= UNSIGNED(sensor_sv) ; D_sv <= STD_LOGIC_VECTOR(D_un) ;

v_1 : t_control port map

(T_in1_un,T_in2_un,sensor_un, Clk_core, rd_fifo_sv(0), reset_sv(0),D_un, oe_b) ;

end ;


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