11.9   Logic-Gate Modeling


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11.9   Logic-Gate Modeling

Verilog has a set of built-in logic models and you may also define your own models.

11.9.1   Built-in Logic Models

Verilog's built-in logic models are the following primitives [Verilog LRM7]:

  • and, nand, nor, or, xor, xnor

You may use these primitives as you use modules. For example:

module primitive;
nand (strong0, strong1) #2.2
  Nand_1(n001, n004, n005),
  Nand_2(n003, n001, n005, n002);
nand (n006, n005, n002);
endmodule

This module models three NAND gates (Figure 11.2). The first gate (line 3) is a two-input gate named Nand_1 ; the second gate (line 4) is a three-input gate named Nand_2 ; the third gate (line 5) is unnamed. The first two gates have strong drive strengths [Verilog LRM3.4] (these are the defaults anyway) and 2.2 ns delay; the third gate takes the default values for drive strength (strong) and delay (zero). The first port of a primitive gate is always the output port. The remaining ports for a primitive gate (any number of them) are the input ports.

 

FIGURE 11.2  An example schematic (drawn with Capilano's DesignWorks) to illustrate the use of Verilog primitive gates.

Table 11.5 shows the definition of the and gate primitive (I use lowercase 'and' as the name of the Verilog primitive, rather than 'AND' , since Verilog is case-sensitive). Notice that if one input to the primitive 'and' gate is zero, the output is zero, no matter what the other input is.

TABLE 11.5    Definition of the Verilog primitive 'and' gate.

'and'

0

1

x

z

0

0

0

0

0

1

0

1

x

x

x

0

x

x

x

z

0

x

x

x

11.9.2   User-Defined Primitives

We can define primitive gates (a user-defined primitive or UDP) using a truth-table specification [Verilog LRM8]. The first port of a UDP must be an output  port, and this must be the only o utput port (we may not use vector or inout ports):

primitive Adder(Sum, InA, InB);
output Sum; input Ina, InB;
table 
// inputs : output
00 : 0;
01 : 1;
10 : 1;
11 : 0;
endtable 
endprimitive

We may only specify the values '0' , '1' , and 'x' as inputs in a UDP truth table. Any 'z' input is treated as an 'x' . If there is no entry in a UDP truth table that exactly matches a set of inputs, the output is 'x' (unknown).

We can construct a UDP model for sequential logic by including a state in the UDP truth-table definition. The state goes between an input and an output in the table and the output then represents the next state. The following sequential UDP model also illustrates the use of shorthand notation in a UDP truth table:

primitive DLatch(Q, Clock, Data);
output Q; reg Q; input Clock, Data;
table 
//inputs : present state : output (next state)
1 0 : ? : 0; // ? represents 0,1, or x (input or present state).
1 1 : b : 1; // b represents 0 or 1 (input or present state).
1 1 : x : 1; // Could have combined this with previous line.
0 ? : ? : -; // - represents no change in an output.
endtable 
endprimitive

Be careful not to confuse the '?' in a UDP table (shorthand for '0' , '1' , or 'x' ) with the '?' in a constant that represents an extension to 'z' (Section 11.2.4) or the '?' in a case statement that represents don't care values (Section 11.8.1).

For sequential UDP models that need to detect edge transitions on inputs, there is another special truth-table notation (ab) that represents a change in logic value from a to b . For example, (01) represents a rising edge. There are also shorthand notations for various edges:

  • * is (??)
  • r is (01)
  • f is (10)
  • p is (01), (0x), or (x1)
  • n is (10), (1x), or (x0)
primitive DFlipFlop(Q, Clock, Data);
output Q; reg Q; input Clock, Data;
table 
//inputs : present state : output (next state)
r    0 : ? : 0 ; // rising edge, next state = output = 0
r    1 : ? : 1 ; // rising edge, next state = output = 1
(0x) 0 : 0 : 0 ; // rising edge, next state = output = 0
(0x) 1 : 1 : 1 ; // rising edge, next state = output = 1
(?0) ? : ? : - ; // falling edge, no change in output
? (??) : ? : - ; // no clock edge, no change in output
endtable 
endprimitive


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