Suppose we have a pushbutton switch connected to the input of an FPGA as shown in Figure 6.11 (a). Most FPGA input pads are directly connected to a buffer. We need to ensure that the input of this buffer never floats to a voltage between valid logic levels (which could cause both n -channel and p -channel transistors in the buffer to turn on, leading to oscillation or excessive power dissipation) and so we use the optional pull-up resistor (usually about 100 k W ) that is available on many FPGAs (we could also connect a 1 k W pull-up or pull-down resistor externally).
Contacts may bounce as a switch is operated ( Figure 6.11 b). In the case of a Xilinx XC4000 the effective pull-up resistance is 5–50 k W (since the specified pull-up current is between 0.2 and 2.0 mA) and forms an RC time constant with the parasitic capacitance of the input pad and the external circuit. This time constant (typically hundreds of nanoseconds) will normally be much less than the time over which the contacts bounce (typically many milliseconds). The buffer output may thus be a series of pulses extending for several milliseconds. It is up to you to deal with this in your logic. For example, you may want to debounce the waveform in Figure 6.11 (b) using an SR flip-flop.
A bouncing switch may create a noisy waveform in the time domain, we may also have noise in the voltage level of our input signal. The Schmitt-trigger inverter in Figure 6.12 (a) has a lower switching threshold of 2 V and an upper switching threshold of 3 V. The difference between these thresholds is the hysteresis , equal to 1 V in this case. If we apply the noisy waveform shown in Figure 6.12 (b) to an inverter with no hysteresis, there will be a glitch at the output, as shown in Figure 6.12 (c). As long as the noise on the waveform does not exceed the hysteresis, the Schmitt-trigger inverter will produce the glitch-free output of Figure 6.12 (d).
Most FPGA input buffers have a small hysteresis (the 200 mV that Xilinx uses is a typical figure) centered around 1.4 V (for compatibility with TTL), as shown in Figure 6.12 (e). Notice that the drawing inside the symbol for a Schmitt trigger looks like the transfer characteristic for a buffer, but is backward for an inverter. Hysteresis in the input buffer also helps prevent oscillation and noise problems with inputs that have slow rise times, though most FPGA manufacturers still have a restriction that input signals must have a rise time faster than several hundred nanoseconds.
Figure 6.13 (a) and (b) show the worst-case DC transfer characteristics of a CMOS inverter. Figure 6.13 (a) shows a situation in which the process and device sizes create the lowest possible switching threshold. We define the maximum voltage that will be recognized as a '0' as the point at which the gain ( V out / V in ) of the inverter is –1. This point is V ILmax = 1V in the example shown in Figure 6.13 (a). This means that any input voltage that is lower than 1V will definitely be recognized as a '0', even with the most unfavorable inverter characteristics. At the other worst-case extreme we define the minimum voltage that will be recognized as a '1' as V IHmin = 3.5V (for the example in Figure 6.13 b).
Figure 6.13 (c) depicts the following relationships between the various voltage levels at the inputs and outputs of a logic gate:
The voltages, V OHmin , V OLmax , V IHmin , and V ILmax , are the logic thresholds for a technology. A logic signal outside the areas bounded by these logic thresholds is “bad”—an unrecognizable logic level in an electronic no-man’s land. Figure 6.13 (d) shows typical logic thresholds for a CMOS-compatible FPGA. The V IHmin and V ILmax logic thresholds come from measurements in Figure 6.13 (a) and (b) and V OHmin and V OLmax come from the measurements shown in Figure 6.2 (c).
Figure 6.13 (d) illustrates how logic thresholds form a plug and socket for any gate, group of gates, or even a chip. If a plug fits a socket, we can connect the two components together and they will have compatible logic levels. For example, Figure 6.13 (e) shows that we can connect two CMOS gates or chips together.
Figure 6.13 (f) shows that we can even add some noise that shifts the input levels and the plug will still fit into the socket. In fact, we can shift the plug down by exactly V OHmin – V IHmin (4.5 – 3.5 = 1 V) and still maintain a valid '1'. We can shift the plug up by V ILmax – V OLmax (1.0 – 0.5 = 0.5 V) and still maintain a valid '0'. These clearances between plug and socket are the noise margins :
For two logic systems to be compatible, the plug must fit the socket. This requires both the high-level noise margin (V NMH ) and the low-level noise margin (V NML ) to be positive. We also want both noise margins to be as large as possible to give us maximum immunity from noise and other problems at an interface.
Figure 6.14 (a) and (b) show the logic thresholds for TTL together with typical CMOS logic thresholds. Figure 6.14 (c) shows the problem with trying to plug a TTL chip into a CMOS input level—the lowest permissible TTL output level, V OHmin = 2.7 V, is too low to be recognized as a logic '1' by the CMOS input. This is fixed by most FPGA manufacturers by raising V OHmin to around 3.8–4.0 V ( Figure 6.14 d). Table 6.1 lists the logic thresholds for several FPGAs.
To reduce power consumption and allow CMOS logic to be scaled below 0.5 m m it is necessary to reduce the power supply voltage below 5 V. The JEDEC 8 [ JEDEC I/O] series of standards sets the next lower supply voltage as 3.3 ± 0.3 V. Figure 6.15 (a) and (b) shows that the 3 V CMOS I/O logic-thresholds can be made compatible with 5 V systems. Some FPGAs can operate on both 3 V and 5 V supplies, typically using one voltage for internal (or core) logic, V DDint and another for the I/O circuits, V DDI/O ( Figure 6.15 c).
There is one problem when we mix 3 V and 5 V supplies that is shown in Figure 6.15 (d). If we apply a voltage to a chip input that exceeds the power supply of a chip, it is possible to power a chip inadvertently through the clamp diodes. In the worst case this may cause a voltage as high as 2.5 V (= 5.5 V – 3.0 V) to appear across the clamp diode, which will cause a very large current (several hundred milliamperes) to flow. One way to prevent damage is to include a series resistor between the chips, typically around 1 k W . This solution does not work for all chips in all systems. A difficult problem in ASIC I/O design is constructing 5 V-tolerant I/O . Most solutions may never surface (there is little point in patenting a solution to a problem that will go away before the patent is granted).
© 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites: