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HDL Chip Design
Author: Smith, Douglas J.

Cover: Hard cover
Pages: 448
List Price: $65.00
Published by Doone Publications
Date Published: 06/1996
ISBN: 0965193438


ASIC and FPGA VHDL/VERILOG design and RTL modeling guide. Characterizes ASICs and FPGAs, discusses synthesis constraints and optimization. Introduces HDL/VERILOG language fundamentals and structured design concepts. Explains modeling of combinatorial, synchronous logic circuits and details finite state machine modeling. Describes how to write test harnesses and gives modeling examples. Very good chapter on design/modeling recommendations, issues & techniques. A unique feature of this publication is the use of complete VHDL code on the left side of a page with the same VERILOG code on the right. Example diskette available by order. Very good tutorial, user's guide and reference. Recommended.