# Logic Design for Array-Based Circuits

### by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White

# Power Considerations

Last Edit July 22, 2001

## AC Power

The dominant source of AC power (~90%) in a CMOS device is due to the charging and discharging, i.e., switching, of the circuit capacitance. AC power due to switching is composed of interface macro AC power and internal macro AC power dissipation. These groups may in turn be broken down by macro type and switching frequency, depending on the particuar array specifications.

The equation for AC switching power for a single device depends on the frequency (f) at which the logic is switching. It is based on the charging of a capacitor (C) to a voltage (V) through a P-channel device to build up a charge (CV). The energy stored is CV2. The energy is in turn discharged through the paired N-channel device.

P = f * C * V2

A variation of the equation is possible when the vendor specifies a constant in terms of microwatts/gate-MHz. The equation can reduce to:

P = 0.20* (a*f*G) (per class of macro)

where .20 is 20% devices switching, a is the power constant in mw/gate-MHz, f is the switching frequency and G is the number of gates.

All devices in a circuit will not be switching at the same time. Estimates from 18-36% devices switching can be obtained from the different vendors, based on the ratio of register elements in the circuit. Loosely, 20% or 30% devices switching is the number used by most vendors.

The equation may be changed to be number of macros with an adjustment in the constant, or it may be specified using .30 as the percentage of devices switching.

Whatever is used in the vendor documentation, the equation represents an estimate of the worst-case AC power.

All devices will not be switching at the maximum frequency. If the frequencies are clearly defined, the problem may be handled as a series of equations, one for each frequency group. In that case, the largest number of elements switching at the same time in that group would be used rather than a 20% estimate. The sum of the power computations for all groups is a worst-case estimate. The factors in the AC power computation are shown in Table 7-3.

Table 7-3 Components Of AC Power Computation

Components of AC Power
• Percent elements switching
• Maximum switching frequency
• Capacitance
• Constant in mW/gate-MHz

CMOS circuits use AC power computation for internal and interface macros. BiCMOS circuits use AC power for their internal macros. The high-speed bipolar circuits will require that an AC power component be computed for their internal and some of their interface macros. Interface macro AC power computations may require input macro and output macro contributions to be computed separately, depending on the methods used by the vendor to specify them. Macros contributing to AC power are listed in Table 7-4.

Table 7-4 AC Power Computation

AC Power Computation
• interface macro AC power
• input macros
• output macros
• internal macro AC power

### Hardware Assist

While it is relatively easy to compute the switching frequency of the interface macros, allowing a realistic value to be computed for their AC power component, computation of internal macro AC power dissipation is more difficult.

Some hardware emulation systems such as IKOS and ZYCAD are providing support for internal macro switching frequency computation and the quality and quantity of the support should expand over the next few years.

### Benchmark Required

Hardware-assisted AC power computations depend on the accuracy of the at-speed vector set. The at-speed vectors must correctly benchmark the expected lifetime behavior of the circuit for these systems to provide accurate AC power computation support.

If the vector set is not accurate, i.e., if the switching patterns are not a correct representation of the expected behavior of the circuit in use, the results can be considered to be no more accurate than the results produced from the estimation equations.

## Worst-case Power

The worst-case maximum power dissipation is required to allow the computation of the worst-case maximum junction temperature. The resulting computation of the junction temperature may allow a reduction in the worst-case IEE current, reducing the DC power. This may in turn affect the junction temperature. The computation of the junction temperature is an iterative process.

The worst-case power as related to junction temperature is used to examine the packaging and the heat-sink requirements of the final product. The worst-case maximum junction temperature is used to evaluate package selection and to make cooling decisions such whether to use a heatsink and what rate of airflow is required.

IEE <==> DC POWER <==> Junction Temperature <==> IEE

Again, this is an iterative process. The package selected will determine the thermal coefficients which affect the choices of heatsinks. Airflow alters the effective thermal coefficients. All of these items affect the final junction temperature.

Figure 7-1 Iterative Power Interactions

 power dissipation <-----------> junction temperature <-----------> package heatsink airflow

### Adjustment Multiplier for DC Power

If the vendor specified power for the individual macros, then the typical power listed with each macro assumes a certain set of conditions including supply voltage. When a different supply is used, an adjustment to the typical power must be made.

The default supply voltage is -5.2V in an AMCC ECL array. In this case the power supply adjustment factors would be as shown in Table 7-5.

Table 7-5 DC Power Voltage Adjustment

Factor Type Supply
1.00 ECL 10K -5.2V
0.96 TTL +5.0V
0.88 ECL100K -4.5V

Some vendors specify an adjustment factor to be used to compute worst-case DC power dissipation from the typical DC power dissipation. For ECL and BiCMOS arrays, the range is 0.6 to 0.7 times typical to find an estimate of minimum power and 1.3 to 1.54 times typical to find maximum worst -case power. This adjustment factor is also called a worst-case multiplier. It may vary between commercial and military grade circuits.

The worst-case multiplier is used with macros that are specified with typical current and with macros that are specified with typical power. When typical current has been specified, this adjustment factor may be called a worst-case current multiplier.

Table 7-6 DC Power Worst-Case Adjustment Factors - Worst Case Multiplier

DC Power Worst-Case Adjustment Factors -
Worst Case Multiplier
0.6-0.70 MINIMUM
1.4-1.54 MAXIMUM

These multipliers may be expected to decrease as newer and cooler arrays are developed.

### Checking with the Vendor

When a designer is evaluating power while selecting an array, the design manual for that array must be reviewed for the items listed in Table 7-7.

### Example 1

AMCC specifies macros with a typical current. To compute power for a Q5000 Bipolar Series based mixed-mode ECL 10K/TTL military circuit, perform the following steps.

• The sum of all IEE and ICC currents, including overhead is computed.
• The currents are multiplied by 1.4, the worst-case current multiplier for commercial and military circuits. [AMCC value]
• The voltage sources of -5.2V and +5V are allowed to vary ±5% for a commercial circuit and ±10% for a military circuit. The -5.2V supply would be -5.72V worst-case maximum and the +5V TTL supply would be 5.5V.
• A separate computation is made for terminated ECL outputs. If all outputs are standard 50ohm terminations, PECL = 1.3 * 14 * n, where n is the number of such outputs.
• Add PEE, PCC and PECL to find the worst-case maximum DC power dissipated by the circuit.

### Example 2

Raytheon specifies power components for its macros. After adjusting for the correct voltage, the typical DC power is the sum of the DC power components of the internal macros, I/O macros and bias cells (overhead). A worst-case multiplier of 1.4 is used to find the worst-case maximum power dissipated by the circuit.

Table 7-7 Topics For Review

Review Topics
• What is specified for a macro?
• current
• typical
• worst-case
• power
• AC
• DC
• adjustments
• for voltage variation
• for temperature variation
• for process variation
• for different operating environments
• How are bias circuits (overhead circuits) to be handled?
• How is power to be worst-cased?
• current multiplier?
• voltage multiplier?
• power multiplier?
• What about TTL outputs on a CMOS array?
• Refinements to this include:
• Power-down of terminated outputs
• Three-state output current variations
• Two-state output current variations
• Junction temperature effects on IEE
• Placement-sensitive overhead or bias current

### Example 3

AMCC specifies typical current for the Q20000 high-speed bipolar series. In this case, there are different worst-case current multipliers, one for internal macro current, one for interface macro current and one for the bias or overhead current.

### Example 4

Several BiCMOS vendors specify an overhead current that is placement dependent or at least usage dependent. The overhead current will have some basic value that is always present as when TTL can be on the array with ECL, and there will be a variable component. The amount of the variable component depends on how many ECL inputs and ECL outputs are used by the circuit, and may depend on where on the array perimeter these macros are placed.

Before placement, the designer should estimate this variable as the worst it could be and make thermal decisions using this value. Refinements in power reduction would include a post-layout review of the overhead current component.

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com