Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Timing Analysis for Arrays
Last Edit July 22, 2001
Before schematic capture, computation of the propagation delays due to loading in a circuit can be performed using a table of statistically derived metal loads (Lnet) for a given net size.
After schematic capture, Front-Annotation software is available to provide the designer with a file of rising and falling edge delays per net expressed as NOM, MIN and MAX, or as a min/max range to represent the uncertainty spread within a given operating condition. Output loading will be based on customer-described system loads and estimated package-pin capacitance.
For EWS systems that can handle ambiguity testing, this allows an evaluation of the uncertainty window propagated down a path. There are six delays for each net. By incorporating these delays into the simulation database, the designer can obtain a statistical estimate of the circuit performance.
Front-Annotation software is resident on individual workstations. It is linked into the workstation's model library by way of an EWS-specific command procedure and is used directly in the simulation database. The resulting simulation output file is the result of both intrinsic and extrinsic delays.
Front-Annotation results cannot be guaranteed. They cannot be used as specifications for the final circuit. Indeed, if they are within 10% of the circuit target specification, the path should be evaluated for further optimization to reduce its delay.
Any path this close to the specification at Front-Annotation time should be called out in the design submission package for special handling and possible preplacement. As stated before, preplacement should never be assumed to be able to solve a timing problem.
Remedial Steps - When a path is too slow
When a path is already too slow by Front-Annotation simulation results, the designer must stop and address the problem before committing more time to simulation and submission requirements. A path that appears to be on the borderline of meeting specification requirements must also be reviewed for possible changes.
Table 5-6 Methods For Speed Improvement
When a circuit is borderline in its performance, Intermediate Annotation may be available to refine the design. It can identify paths that are already in trouble or that are borderline that were not identified in the pre-placement Front-Annotation analysis.
The use of the Intermediate-Annotation delay file in a re-simulation is cost-effective since it allows placement changes to be made before entering the costly routing process. (AMCC used this for problem circuits on an in-house only basis for some time.)
Intermediate-Annotation uses the same electrical loading delays as Front-Annotation but it has a refinement on the delays due to metal length. One program uses the placement file and the Manhatten Distance Algorithm and closely approximates the results that will be seen in Back-Annotation. The accuracy of the algorithm varies with the net size.
Values for the loading delays on the output macros will reflect the same customer-defined system load but will now include actual package-pin capacitances, providing a further refinement in the timing analysis.
To allow more control at the customer site, some ASIC companies are making packaging databases available to the annotation procedure. Combined with a basic placement capability, this allows the intermediate annotation to be available at the customer's site before any simulations have been performed. It improves the trial-and-error or alternate solution analysis by providing more accurate data.
Note that Intermediate-Annotation results still cannot be guaranteed. They cannot be used as specifications for the final circuit.
Remedial Steps - Intermediate-Annotation
When a path is too slow by Intermediate-Annotation simulation results, the designer must again stop and address the problem before committing more time to simulation and submission requirements. A path that appears to be on the borderline of meeting specification requirements must also be reviewed for possible changes. The procedures followed are the same as those listed for Front-Annotation timing problems.