Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Sizing the Design - Selecting the Array
Last Edit July 22, 2001
Final Interface Cell Utilization
The final interface cell count for the circuit in its estimated stage should look at all the factors that could increase interface cell requirements. The interface cell utiliza tion for a non-captured circuit should be less than 100% if possible to allow for adjustments and expansion. If this is not possible, than the rest of the design must be completed using I/O cell utilization minimization as a priority design objective.
In the ideal situation, an array chosen for a design should be somewhere in the middle of an array series. This is to provide a smaller option if I/O minimization can reduce the requirements and to provide a larger option should the interface requirements grow out of the original selection.
If not, then the interface utilization should be no more than 90% during develop ment, with no more than 100% interface utilization for the final design.
Interface Cell Utilization (general)
To find interface cell utilization, add the items in the list in Table 3-18.
Table 3-18 Interface Cell Utilization
Divide this sum by the number of interface cells available on the array of choice.
Interface cell utilization = (number of interface cells used by the circuit) / (number of interface cells available on the array)
Example - BiCMOS Cell/PAD Utilization
When an array does not have a one-to-one ration of I/O cells and pads, then PAD utilization may also be required. The Q24008 and Q24280 arrays have 2-cell-1-pad structures. Certain macros placed on these structures are very efficient, others are not. Depending on the macros used, single-cell or multi-cell, either pads or cells may be rendered inaccessible. These arrays have a complex algorithm available to allow sizing. The algorithm requires a check on both cells and pads.
PAD utilization = (number of PADS used by the circuit) / (number of PADS available on the array)
Fan-out load limits
Internal cell usage will depend on the macros required to implement the desired func tions. Refinements to that estimate come when the fan-out load limits, hook-up and pin restrictions for those macros are evaluated. If an interface macro is driving too many loads, internal macro buffers will be needed to divide that load or additional interface macros will be needed. If internal macros are driving too many loads, the same approach is used. These buffer trees use cells and current.
Macros will be specified with both fan-in and fan-out load limits. The fan-in numbers represent the load that the macro presents to the macro driving it. The fan-out limit is the number of loads that the macro can safely drive before signal degradation becomes a predominant factor. A load unit can be considered to be equivalent to one pico-farad. Check with the array vendor for their definition.
Derated fan-out load limits
Clock paths, distortion-sensitive and high-speed paths should be designed with a derated fan-out load limit, i.e., with macros operating well below their specified limits. The array may be specified with a guideline as to the frequency - derating schedule.
Each AMCC array series is different in the value of the breakpoint frequency but each has the same basic rule. For sensitive and clock paths, derate the fan-out load limit by 20% up to the breakpoint and 40% at or above the breakpoint frequency.
Example - fan-out derating
For the Q20000 Series, all internal macros have the Turbo speed enhancement allow ing a fan-out load limit of 18 loads. The TTL input and bidirectional input macros are the only interface macros that do not have this Turbo enhancement and their fan-out load limit is 9 loads.
Assume that the breakpoint frequency is currently set at 400MHz.
For an ECL input toggling at 500MHZ, the derated fan-out load limit would