Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Last Edit March 13, 2002
If a standard simulation vector format; is required by the array vendor or by software to which the simulation results must be submitted as data, some means of reformatting must be available. For arrays, the functional, parametric, and AC test simulation results are generally used as input to test vector generation; software, and the allowed input formats may be restricted.
AMCC accepts only binary results for specific signals (input, output, bidirectional, 3-state and bidirectional enable internal signals). Sample size is restricted. No print on change; results are used for functional simulations, only sampled. No waveforms are requested.
Since there are different simulation output formats, AMCC customers use a reformatter to translate Dazix, MENTOR, Verilog, Lasar and VALID simulation output files into a generic format;. If any other workstation is used, the output of that simulator must also be reformatted. AMCC uses their AMCCSIMFMT; software to transpose output files into an AMCC generic interface format that their test software programs can read.
Regardless of the implementation selected, the design must be simulated and the parts tested. There may be a number of functional, parametric and AC test simulation vector rules; that must be followed to insure correctness in the test program. The rules are based on tester limitations;, test procedures and test objectives. The rules required by the array vendor must be clearly stated and it is increasingly desirable to have some form of rules check software available to help the designer.
AMCC supplies a vector checker, AMCCVRC;, to catch the more blatant vector rule violations such as missing required signals, too many signals switching in one vector causing noise, race conditions, undesired internal signals in the output and uneven sampling steps. Some basic toggle tests are also included.
The design submission process for custom and semi-custom arrays requires a number of specific forms, files and validation procedures be followed and the process is increasingly complex. Automation of that procedure is one desirable goal. Automation support is feasible for the I/O signal list;, package pad-pin-post, capacitive load; and I/O toggle frequency; descriptions, design validation; checklists and design submission; checklists, including simulation submission.If no automated support is available, the necessary forms must be reviewed and filled in manually. Errors and incomplete information can lead to schedule delays. (Refer to the framework systems.)
As a part of the submission process for custom and semi-custom arrays, the designer may wish to submit a desired placement or partial placement. The vendor must supply placement; rules and restrictions for the particular array in the selected package as well as a placement worksheet.
The user may be able to choose between a full graphic interface to the placement system or be content to supply the vendor with an ASCII list for placing some or all the macros, and let the vendor complete the placement process.
The options and the control over placement become an issue when performance is driven to the limits of the array technology. I/O placement is an issue when an array will emulate an older technology and the PC board array pin out pattern must remain unchanged.