Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White



Last Edit July 22, 2001

Process Examples

Any process selected must be one that will still be in use in five years, a rational window for a design life. There have been process technologies; that came into existence and left in a shorter window, leaving prototyped designs with no access for production. A reliable, proven process is the better choice. Process variations for the series below center on isolation techniques. (Figure 1-5.)

€ The process used for the older Q700 and Q1500 Series Logic arrays was diffusion/junction isolated;, with a 5 micron washed emitter. The smaller emitter was obtained because it was self-alligned. This array series was prefabricated on a P-substrate and used two-layer metalization.

€ The process used by the Q3500 Series arrays is a 3 micron oxide-isolated; process with two-layer metalization for the customization. The Q3500 achieved twice the speed of the Q1500 and Q700 arrays.

Figure 1-4d Relations among Technologies

€ The process used by AMCC for the Q5000 series is 2 micron oxide-isolated. It is the same process that was used for the earlier Q3500 Series arrays, linearly scaled by 0.80 with an interface redesign. The Q5000T array itself uses three metal layer customizations while the rest of the arrays in the series use two layer metal.

€ A newer bipolar array series, marketed by AMCC as the Q20000 Series, uses a trench isolated; Bipolar process (TOI) with an AMCC-patented ECL circuit technique for high speed and lower power. It uses the same sea-of-cells; architecture as the BiCMOS arrays. First layer metal is used for intra-macro routing; and I/O to core routing. Second and third layer metal are used for inter-macro interconnect, but this can vary. The speeds achievable by these new arrays is observed to be between 1.2 and 1.25GHz.

€ The process used for the Q14000 Series BiCMOS arrays is 1.5 micron CMOS with 1.5 micro oxide-isolated bipolar process on a single silicon chip.

The BiCMOS process uses an N-epitaxial layer as the foundation for both NPN bipolar and CMOS devices. The CMOS transistors are used for logic implementation only and therefore use devices that are smaller than those required for a pure CMOS array. Bipolar totem-pole device pairs are used to provide the needed drive capability between logic cells. The I/O cells are bipolar. The Q14000 Series arrays (Q28000B, Q14000B, Q6000B and Q800B) use a sea-of-cells architecture.

Figure 1-5 Isolation Techniques (early 1990s)

Physical separation must be maintained
between the p+ region used as part of the
isolation layer and the buried layer

Lower alignment tolerances (oxide is inert);
greater packing densities; can run
conductors among the transistors in the oxide

Note: The process used for the Q24000 Series BiCMOS arrays is 1.0 micron CMOS with 1.5 micro oxide-isolated bipolar process on a single silicon chip. It is identical in all other features to the Q14000 Series but was faster.



Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
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