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Posts Tagged ‘Vigyan Singhal’

Oski Technology: Establishing the Decoding Formal Club

Thursday, October 24th, 2013

 

If you are someone who does formal verification and is looking for a chance to talk over the challenges with others who do similar work, Oski Technology has something that may be of interest to you. Starting this month in Silicon Valley, the company is kicking off its Oski Decoding Formal Club. The inaugural meeting took place at the Computer History Museum on October 10th, and was lead by company CEO Vigyan Singhal.

Over lunch, he presented a 45-minute overview titled, “Using Bounded Proofs in Formal Sign-off.” Singhal noted during his talk that it’s the reality today that formal is expensive and returns “low bang for the bucks.” He insisted, however, that if there were places to learn more about how to apply formal verification, and how to build a productive formal team, the technology would be more widely applied and its destiny more quickly fulfilled as an extremely effective technique for use end-to-end throughout the design process.

Following Singhal’s presentation, the 20+ people in attendance (representing 10 companies) were each given time in a relaxed, roundtable environment to share their experiences and/or frustrations with formal. The companies included Apple, Broadcom, Cisco, HiSilicon, Memoir Systems, Microsoft, Nvidia, Palo Alto Networks, Qualcomm, and a startup. In other words, companies both big and small were represented and the resulting conversation was very interesting. It was clear as the talking stick was handed around, that some practitioners were very confident and sure of themselves, while others were relieved to know they’re not the only ones who struggle with formal.

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DVCon 2013: Best Practices in Verification Planning

Thursday, February 28th, 2013

 

Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of “Best Practices in Verification Planning.”

Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous. The Cadence-sponsored lunch and panel discussion, moderated by Cadence’s John Brennan, included Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan. The panelists began with an overview of their experiences.

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Oski Technology: 72-hour Live Verification Challenge

Wednesday, September 12th, 2012

 

This is a great story: Oski Technology decided to prove the validity and efficiency of Formal Verification, and proposed a public challenge for themselves at DAC – a 72-hour window of time in San Francisco whereby they would attack a design problem never before seen, analyze it, propose a verification plan, and execute on that plan between 5 pm on DAC Sunday and 5 pm on DAC Wednesday.

To get a design problem, Oski Technology put out a request for proposal to different companies. The design could be at any stage in development, but had to include the RTL and some level of specifications for what the architecture should do, as well as some simulations.

Among the 5 respondents, Nvidia’s suggested problem was the most appropriate: It was a design that was still not complete and needed verification. More importantly, Nvidia was not afraid to have possible bugs or flaws in the design made public, a sign of their own confidence. So at 5 pm on Sunday, June 3rd, the Oski Technology team opened the files provided by Nvidia.

I’ll let Vigyan Singhal, Oski Technology’s President and CEO, take the story from there in his own words. Vigyan and I spoke by phone on September 12th, the same day a 6-minute video of the whole process was made available by the company. [Here’s the link on YouTube.]

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The challenge …

Per Vigyan Singhal: “We had gotten the design in advance from the verification manager at Nvidia, but couldn’t even look at the documentation until 5 pm on Sunday, let alone the RTL files. Then after we opened everything, we looked at the code and the design specifications and went from there.

“Initially during the first night and the next morning, we were mostly doing planning. As we learned more about the design, as is usual with this type of thing, we found some unexpected things. Some of the sub-modules were missing from the design. Nvidia had given us the simulation waves, however, so we could guess the functionality and from there wrote Verilog for those little modules.

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