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Posts Tagged ‘Verilab’

D&VCon: A labor of love for Krolikoski & Co.

Thursday, February 13th, 2014

 

If ever there was a year when you thought to attend DVCon, this should be it, according to a recent phone call with Cadence Fellow Stan Krolikoski, serving as General Chair for the second year in a row. That’s because DVCon 2014 will be serving up the D and the V in equal measure, and won’t be skewed towards the V in DVCon as it has been [perhaps] in the past.

Per Stan, “We’ve gotten feedback every year from attendees that they want more emphasis on design. They say they like verification, but they want more design, so last year I gave marching orders to the Technical Program Committee [headed by Paradigm Works’ Ambar Sarkar] that they should add more people on the review committee who represent design.

“It’s actually been a long time in coming. Although last year was the 25th anniversary of the conference, 10 years ago the name was changed to DVCon. Prior to that, it was HDLCon and the content reflected that name. When the name was changed to DVCon it was supposed to include both design and verification, but [functional verification emerged as the larger focus].”

That focus meant that those types of experts tended to dominate attendance, according to Stan, but that’s been fixed this year: “We will still have excellent functional verification sessions at DVCon – everything for the beginner through to the guru, it’s all there – but we will also have sessions on low-power design, on analog/mixed signal, and on system-level design, as well as IP integration. We’re clearly moving away from just verification in adding lots of design content to the program that’s of interest to our audience.”

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DVCon 2013: Best Practices in Verification Planning

Thursday, February 28th, 2013

 

Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of “Best Practices in Verification Planning.”

Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous. The Cadence-sponsored lunch and panel discussion, moderated by Cadence’s John Brennan, included Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan. The panelists began with an overview of their experiences.

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Pop Quiz: The Standards Game

Friday, February 17th, 2012

 

Here’s your February Pop Quiz.

******************

1 – DVCon 2012 starts on February 27th. The conference was first held in _____.

a) 1989
b) 1995
c) 1998
d) 2003

2 – The IEEE Standards Association [IEEE-SA] oversees approximately _____ standards and _____ standards under development.

a) 500, 900
b) 800, 600
c) 900, 500
d) 700, 900

3 – The IEEE Standard associated with VHDL is _____.

a) IEEE Std 1064
b) IEEE Std 1076
c) IEEE Std 1164
d) IEEE Std 1176

4 – Accellera merged with _____ in 2011.

a) VSIA
b) OSCI
c) OCP-IP
d) OVI

5 – DVCon is managed by MP Associates, the same group that manages _____.

a) ICCAD
b) DesignCon
c) Semicon
d) ISQED

6 – The 2007 General Chair of DVCon was _____.

a) Tom Fitzpatrick
b) Stephen Bailey
c) Shankar Hemmady
d) Gabe Moretti

7 – SystemVerilog was donated to Accellera in _____.

a) 2000
b) 2001
c) 2002
d) 2003

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