Open side-bar Menu
 What Would Joe Do?

Posts Tagged ‘Verific’

EDA loses an Advocate: Bob Gardner will be sorely missed

Thursday, April 13th, 2017

 


Every industry needs advocates
, and Bob Gardner served with distinction in that role for many years. When he passed away this week, the industry lost both an articulate spokesman, and someone who had a deep and nuanced understanding of how the unique group of companies involved in EDA and IP come together to provide the crucial underpinnings of a global semiconductor design chain.

Gardner’s most important industry-wide contributions, of course, came during his eight years as Executive Director of the EDA Consortium. He had, however, many years of leadership and involvement in a variety of companies prior to his EDAC assignment, including roles at Verific, Signetics/Philips, AMD, Exemplar Logic, Design Acceleration, Bridges2Silicon, and ITeX.

Given that background, Gardner was able to bring decades of corporate wisdom to his role at EDAC and used it wisely to help craft the mission and work of the Consortium. During his tenure, the organization expanded its membership, became even more pro-active in promoting the common agenda for member companies, and helped to expand the visibility of EDAC across North America and into Europe and beyond.

(more…)

Invionics: Optimism leads to Innovation

Tuesday, July 29th, 2014

 

There are two ways you could have talked to the young Vancouver-based company Invionics in June. Make your way to British Columbia, or seek them out in the Verific booth at DAC in San Francisco. The second option is how I got to chat with Invionics CEO Brad Quinton, and although our conversation amidst the organized chaos of DAC was brief, it left the impression of a company with a bold future ahead.

Per their website, the company’s products include “design tools, hardware IP and EDA development platforms.” However, Invionics also provides “experienced contract R&D to extend our products and IP, [which enables our] customers to quickly implement key functionality and gain competitive advantage for their products.”

In other words, Invionics is my favorite kind of company: A product company that’s also a services company. Of course, this is my evaluation and not necessarily theirs. Nonetheless, it was completely refreshing to talk to somebody at DAC who seems to look at things with a new perspective, an optimistic perspective that’s all about charting a new path going forward.

(more…)

Blue Pearl: Language Support & Workshops

Thursday, March 15th, 2012

 

If you missed this week’s Blue Pearl Software workshop in Silicon Valley, you’re in luck – they’re holding it again on April 19th.

These workshops offer not only the opportunity to learn about Blue Pearl’s technologies, they’ll also let you brush up on your acronyms – FPGA, ASIC, SOC, CDC, SDC, SV, VHDL, and RTL – though not necessarily in that order.

Blue Pearl sells a suite of tools offering “comprehensive RTL analysis, clock-domain crossing [CDC] checks, and automated Synopsys Design Constraints [SDC] generation for FPGA, ASIC, and SOC designs.”

Release 6.0 was announced in February at DVCon 2012, where I spoke with Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.

Jeeawoody said, “We provide tools for linting, clock-domain crossing, and automated SDC generation – things people use to constrain their synthesis. Here in Release 6.0, a major new feature includes language coverage. (more…)

CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise