Posts Tagged ‘TSMC’
Wednesday, May 15th, 2013
Not all of the 1600+ people who attended DATE 2013 earlier this year in Grenoble were able to fit into the room where the panel celebrating 30+ years of the Mead-Conway VLSI Revolution took place. Those who could, however, were treated to a lively 90 minutes of conversation on what that revolution meant to the world of electronics and chip design.
Organized by Synopsys’ Marco Casale-Rossi and moderated by U.C. Berkeley’s Alberto Sangiovanni-Vincentelli, panelists included Berkeley’s Jan Rabaey, IMEC’s Hugo de Man, CMP’s Bernard Courtois, Columbia University’s Luca Carloni, and Synopsys’ Antun Domic.
Although I was among those disappointed to have missed the event, I was able to speak after the fact with Antun Domic. He described the ambiance of the SRO session in Grenoble and enumerated several of the points laid out by the panelists, starting with their praise of Lynn Conway and Carver Mead’s ground breaking text book, published in 1980, Introduction to VLSI Systems.
Wednesday, April 10th, 2013
As TSMC Chairman and Founder Dr. Morris Chang made his way up the steps and across the stage on Tuesday morning to keynote at the opening of his organization’s 19th annual global tech tour, the ballroom in the San Jose Convention Center was plunged into silence, one imbued with a palpable sense of both reverence and awe. There were easily a thousand people in the room, but nary a sound. It was astonishing.
Chang positioned himself at the microphone centered on the broad stage and then delivered an equally astonishing twenty-minute address, without notes and only one or two slides. First, he acknowledged his audience …
Thursday, April 4th, 2013
Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.
Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.
Thursday, March 28th, 2013
To say this is the year of the finFET is somewhat of an understatement, because everywhere you go somebody’s talking about going up instead of out – at ISSCC, at DesignCon, at DVCon, at ISQED, at SNUG, at EDPS, at DAC.
Among the talks so far, one of the best was given by the father of the finFET himself, U.C. Berkeley’s Chenming Hu. If you were at ISQED in Santa Clara on March 5th, you heard Prof. Hu describe how increasing leakage current in planar devices motivated radical new thinking in the late 1990s: Instead of a classic source, drain, gate structure, take a thin film of high-quality silicon material, place gate-dielectric above and below it such that the silicon is never very far from the gate, and then turn the thing 90 degrees so that the source is out the back, the drain’s in front, and the gate material is vertical.
Thursday, March 21st, 2013
It’s time to start exploring what’s coming up at DAC 2013 in Austin the first week in June, and one way to do that is to visit the conference website. There you’ll find a variety of interesting things including an interactive Exhibit Hall map, which allows you to run your mouse over any booth and see which company’s going to be located there. Maybe that feature’s been available in years past, but it’s still pretty cool.
Something that certainly is new this year at DAC, however, is Innovation Square. I’ve boldly cut-and-pasted the graphic from the DAC website into this blog so you can see what it entails, which is this: You pay the DAC organization $5500 and for that you get a kiosk-like space, a 24-inch computer monitor, an electrical hook-up for your other stuff, booth-unit graphics, a shared private meeting suite with a schedule that you’ll know in advance, and one paid-in-full conference registration.
In other words, you get a “turn key package” that allows you to have a foot on the ground at DAC without enduring the mystery of “What’s this all going to actually cost me?” True, it looks like any particular company in Innovation Square only has about 15 or 20 square feet of show floor, but if otherwise you couldn’t afford to be on the show floor at all in Austin, this is a great innovation indeed.
Thursday, January 3rd, 2013
Last night, Judy Collins gave a holiday concert at Davies Hall in San Francisco to a sold-out crowd of acolytes. Only an artist of Collins’ fame would be allowed to ofttimes warble off-key, forget the occasional lyric, and natter on in and around the music, yet still receive a standing ovation. After all, at 73 she is still full of performing fire, still full of attitude and life. Her appearance at Davies was a celebration of that life, lived to the fullest and in many different spheres.
Last week, U.C. Berkeley’s EECS Department threw a birthday party/symposium for Chenming Hu in Sutardja Dai Hall for an SRO crowd of past students, present students and acolytes, friends and family. Only an educator and technologist of Hu’s stature – former CTO of TSMC, ‘father’ of the FinFET, ‘godfather’ of BSIM and an international expert on CMOS device models – would be honored thusly in his 65th year by the University, and allowed to hand pick the list of speakers who filled the day-long event.
Not the least among those chosen was Ramune Nagisetty, a former MSEE student of Hu’s, who now leads a team at Intel/Hillsboro. Nagisetty recently added self-taught guitarist and vocalist/lyricist to her CV, and no matter that she ofttimes warbled off-key during her lunchtime and mid-afternoon performances during the symposium, and nattered on in and around her music, she still received a jumped-to-their-feet ovation from Hu et al.
That’s because Nagisetty was just one part of the evidence offered on December 13th – talks, demonstrations, and performances – to prove that Chenming Hu’s life to date has been lived to the fullest and in many different spheres: His family was in attendance to celebrate with the crowd, Hu’s paintings, and those of his wife and sons, were on display in the lobby outside Banatao Auditorium, Nagisetty’s music was presented, and a remarkable group of technologists as diverse as …
Thursday, November 1st, 2012
The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.
In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.
Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.
“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.
“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”
Thursday, October 25th, 2012
Montreal is not a place that normally comes to mind when you think of EDA. Space Codesign Systems, however, is on a fast track to change that in a classically Canadian way – calm, cool, and collected.
When I spoke with General Manager Dr. Gary Dare on a beautiful afternoon in Southern France at SAME Forum in early October, he explained how the company started in Canada, and the road map they have set out for themselves: “We’re an EDA company, an EDA startup, and we are definitely based in Montreal. If you doubt that EDA has a place in Canada, we will soon convince you otherwise.
“Space Codesign comes from the acronym, SystemC Partition of ACE, which was the 2004 research project at the Ecole Polytechnique [University of Montreal] that our technology is based on. In 2008, Professor Guy Bois and various graduate students associated with the project decided to do a spin-out, and in 2010 Space Codesign Systems went into operation.”
He laughed and added, “Our company has nothing to do with space, however. But it has everything to do with hardware/software co-design – doing it simultaneously, rather than the usual way of ESL hardware design followed by software design. The audience we are targeting is the systems architects who are looking at the algorithmic level and need a route to design exploration and implementation. Our tools give them that route.
Wednesday, September 5th, 2012
There are thousands of companies based in Silicon Valley, but not all of them focus on the long-term play. Valin Corp. does have that focus, however, intentionally balancing their product portfolio across a range of industries, and investing in their employees with equal intensity.
Company President & CEO Joe Nettemeyer told me in a recent phone call that this strategy has allowed Valin to grow non-stop over the last half-decade: “We’ve achieved growth through a combination of internal development and acquisition, averaging 20-percent growth or more, per year, over the last 5 years, even in spite of a slight hiccup in 2009. We like to invest in industries that are counter-cyclical to each other. When there’s a slow-down in one area, we can cover the slack with revenue in another.
“We’re an infrastructure company working in the wafer-fab-equipment end of the semiconductor industry, designing and building system solutions for companies around the world that make semiconductor-based products. We just completed a project with AKT that makes equipment for large flat-screen panels to retrofit 30 systems for Samsung.
“We’ve also expanded our capabilities in other industries over the years, particularly as a strategic global distributor for Applied Materials. We’re recognized as one of the top 40 industrial distributors in the nation based on our sales revenue, and have just been recognized as one of INC Magazine’s 500/5000 fastest growing companies in America.
Wednesday, August 1st, 2012
When Eric Filseth took over as CEO at Ciranova in September 2007, he was already a seasoned EDA veteran having clocked in an accumulated 17 years at Cadence at that point. Now here in 2012, Ciranova has just been acquired by Synopsys and it would seem Filseth’s organization has fulfilled the vision he articulated 5 long years ago.
Per Filseth in 2007: “The problems in analog are very hard. In the digital world, everything is very, very automated, but in the analog world it just isn’t that way. It’s still mostly done by hand and the concept of IP as you consider it in digital – take the RTL and port it to this design or that process – is not there. In analog, it’s still a manual thing for PLLs, and amplifiers, and so on.
“There’s been so much focus on digital SoCs, and things like place and route, there’s been a lot less time spent on analog. Now digital design works fantastically well. You can get a junior engineer with only a couple years’ experience designing thousands of gates a day.
“Just think about it. Over the last 20 years, we’ve had 4 or 5 generations of digital architectures developed but in analog, people are still doing things the way they did it 15 or 20 years ago. Clearly there‘s an opportunity here, and Ciranova is well positioned to take advantage of that opportunity.”