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Posts Tagged ‘TSMC’

Herb Reiter at EDPS: Multi-Die IC Design and Application

Thursday, March 24th, 2016


To speak with Herb Reiter about the rationale for multi-die packaging
is a chance to follow a logical and energetic continuum from first principles to a final conclusion. Namely, that as the era of the ASIC subsides, the era of the multi-die package will arrive full force.

Reiter, President of eda 2 asic, will be reiterating this line of thinking, in conjunction with a panel of like-minded experts, at the upcoming EDPS conference in Monterey on April 21st. In anticipation of that session – “Multi-Die IC Design and Application” – we spoke by phone this week. The conversation was compelling.


Means, Motives, Opportunity: why TSMC should buy Cadence, the Reunion Tour

Thursday, July 30th, 2015


It’s been 10 years since I first explained why TSMC should buy Cadence. Now a decade on, many things have changed in the world and many have not.

Among the things that have not changed? TSMC still should buy Cadence.

Means …

First of all, let’s look at the numbers (per Yahoo Financials re: 2014):

* Taiwan Semiconductor Manufacturing Co. Ltd.

Employees: 43,500
Market Cap: $166.44 billion
Revenue: $27.31 billion
Operating margin: 39.26%
Net income: $9.70 billion
Total Cash: $16.61 billion on $7.40 billion in debt

* Cadence Design Systems Inc.

Employees: 6,100
Market Cap: $6.14 billion
Revenue: $1.61 billion
Operating margin: 11.23%
Net income: $161.1 million

* Conclusion

TSMC has got the means to buy Cadence.

By a long shot.


#52DAC: Rumors & Realities

Thursday, June 11th, 2015


It’s always hard to capture the spirit of any particular trade show/tech conference when it’s as large as DAC. So here’s just a small sample of the rumors and realities being bandied about at Moscone Center this week in San Francisco.

* Rumor: The Exhibit Hall ran until 7 pm on Wednesday night, so if you wanted to see the bagpipes close out the show, you could see it if you arrived at the Cadence booth by 6:45 pm.

* Reality: The Exhibit Hall closed at 6 pm on Wednesday, not 7 pm as on Monday and Tuesday. The bagpipes closed out the show, but at 6 pm, not 7 pm. Those who missed it were very, very sad.

* Rumor: DAC’s Exhibition Hall has shrunk so much over the last few years, it’s no longer going to be housed at Moscone Center. After next year’s DAC 2016 in Austin, the show’s headed to the San Jose Convention Center in 2017.

* Reality: Moscone Center is being renovated over the next several years, so DAC’s going to be in Austin in 2016, in Austin in 2017, and (probably) back in San Francisco in 2018.


Wild West: OneSpin’s Dave Kelf rides shotgun on SystemC

Monday, March 23rd, 2015


The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run wild free. First however, we caught up with OneSpin and the Cloud.

Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.

“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”


Tanner’s PDK: Pretty Darn Kool

Thursday, October 30th, 2014


Tanner EDA is based in Monrovia, California, which already tells you something about the company. They don’t play by the expected rules in EDA, they’re not based in Silicon Valley, they’re independent-minded, customer-centric, and have a long-time commitment to interoperability and straight-forward messaging.

When I spoke by phone this week with Tanner President Greg Lebsack, I suggested that Tanner is the Madison Bumgarner of EDA – steady, delivering without fanfare, successful and consistently attributing that success to team and hard work, while also expressing respect for the competition in the league.

Lebsack chuckled at the comparison and suggested an L.A.-based pitcher would be a more appropriate Tanner totem, one that wouldn’t get him in hot water with friends and family, but if I couldn’t see past Bumgarner he would reluctantly accept the compliment.

He added, “From the founding of Tanner, we have been a company built by engineers for engineers and taking great pride in our products. Being a small company without the marketing budget of the big companies, it’s true we are a well-kept secret in EDA, but that is changing with more and more people taking notice of us.”


Silicon Cloud: Architecting the Future of Design

Wednesday, July 16th, 2014


Despite its ethereal-sounding name, Silicon Cloud International is a company grounded in the reality of chip design, particularly for an important international demographic, professors and students. Mojy Chian is CEO of the Singapore-based SCI. We spoke recently by phone.

Chian started by defining the cloud. “The concept of the cloud is straightforward. It means remote computing, so if you are not using your local machine, you are using the cloud. There are a lot of applications in the cloud, including eCommerce, Facebook, cloud storage, and remote collaboration based in the cloud.

“Certainly, usage of the cloud has taken off in recent years, but remember there are several different types of clouds. In contrast to private cloud computing, public cloud computing means accessing machines [owned by other companies such as Amazon], where you can actually go and use their machines.”

Our conversation being specific to chip design, I asked Chian to comment on widespread industry concerns regarding security when working in the public cloud. Companies are oft-times reluctant to compute and/or store their designs in the public cloud for fear of losing their precious data to hackers and pirates.


Herb Reiter: The three-legged stool of Technology Choices

Thursday, September 5th, 2013


Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.


Semicon West 2013: a quick sponsor eval

Thursday, July 4th, 2013


A note: Since composing this blog, the terrible crash took place at SFO. This tragedy is being felt keenly in the tech industry as it is possible that some of those on board were coming to San Francisco for Semicon West. Many people at the conference may have a special connection to the injured and/or have had their travel plans radically altered while SFO is attempting to deal with the aftermath. The people at EDACafe wish to express their deep concern for everyone affected by the accident.


This is clearly a holiday week, so most people are paying more attention to the barbeque than next week’s massive Semicon West in Moscone Center, so let’s keep this pre-event note short and to the point.

It is always [somewhat] telling to see who is and who is not sponsoring conferences, and Semicon West is no exception. What can be discerned, for instance, from the fact that GlobalFoundries is a sponsor of the conference this year, but TSMC is not? That Mentor Graphics and Synopsys both have their names on the sponsor list, but Cadence does not?


pre-DAC 2013: TSMC certifies ATopTech, CDNS, MENT, SNPS

Thursday, May 30th, 2013


In the old days, TSMC made a big toolflow announcement every year at DAC, and hosted a lively ‘partner pavilion’ where dozens of companies were showcased in small auxiliary booths that stood in addition to their conventional booths elsewhere in the Exhibit Hall.

At DAC 2103 in Austin, however, something different is happening. Hosted by GlobalFoundries, this year’s ‘foundry pavilion’ will showcase countries, not corporations: “The DAC Global Forum celebrates contributions and future plans of nations around the globe to the field of electronic design in past (sic) 50 years.” Should be very interesting; check out Booth #137 in Austin.

In the meanwhile, TSMC’s taking this week prior to DAC 2013 to announce various tool certifications, including FinFET v0.1 design enablement: “The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology.”

It’s always fun to read through these types of joint announcements, at least if you’re easily amused by the exercise of comparing the quotes embedded in dueling Press Releases. TSMC Senior Director Suk Lee, for instance, is quoted in all four press releases paraphrased below, sent out this week from ATopTech, Cadence, Mentor, and Synopsys.


Antun Domic: in hindsight, Mead-Conway Revolution at DATE

Wednesday, May 15th, 2013


Not all of the 1600+ people who attended DATE 2013 earlier this year in Grenoble were able to fit into the room where the panel celebrating 30+ years of the Mead-Conway VLSI Revolution took place. Those who could, however, were treated to a lively 90 minutes of conversation on what that revolution meant to the world of electronics and chip design.

Organized by Synopsys’ Marco Casale-Rossi and moderated by U.C. Berkeley’s Alberto Sangiovanni-Vincentelli, panelists included Berkeley’s Jan Rabaey, IMEC’s Hugo de Man, CMP’s Bernard Courtois, Columbia University’s Luca Carloni, and  Synopsys’ Antun Domic.

Although I was among those disappointed to have missed the event, I was able to speak after the fact with Antun Domic. He described the ambiance of the SRO session in Grenoble and enumerated several of the points laid out by the panelists, starting with their praise of Lynn Conway and Carver Mead’s ground breaking text book, published in 1980, Introduction to VLSI Systems.


S2C: FPGA Base prototyping- Download white paper

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