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Posts Tagged ‘Synopsys’

Simon Davidmann: A re-energized Imperas Tutorial at DAC

Wednesday, July 19th, 2017

 


Impersas CEO Simon Davidmann lead a tutorial
at the Design Automation Conference last month in Austin. Prior to his presentation, we spoke by phone about the content of that tutorial.

“It’s a simple message we’re presenting at DAC,” Davidmann said, “but an important one. If you’re a semiconductor guy building a chip, your customers want to know what components are being used, but you also have to build the software that runs on top of it.

“There’s a lot of challenge, however, in getting an operating system up and running on the hardware and the problem extends to hardware-dependent software. Even the lowest level bits become part of the operating systems. So our tutorial is about what you need to do this work, about how to get hardware-dependent software running.”

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John Sanguinetti: Grand Challenges in EDA, Chilling Challenges in Security

Thursday, June 1st, 2017

 


Master technologist John Sanguinetti
has made major contributions to the EDA industry in the first decades of his career, and is now doing the same for the IP industry. After finishing his PhD at University of Michigan, Sanguinetti worked at DEC, Amdahl, Elxsi, Ardent Computer, and NeXT, was President at Chronologic, Modellogic, and CynApps, and was CTO at Forte Design.

In 1990 while still at NeXT, Sanguinetti became convinced he could write a better simulator than Cadence’s VerilogXL, so working nights and weekends for several months he wrote VCS. The potential of the tool inspired Sanguinetti and Peter Eichenberger to found Chronologic. They launched the product in late 1992, and sold the company to Viewlogic in late 1994. Synopsys acquired Viewlogic in 1997, and VCS has continued on there as a foundational element of the company’s verification strategy.

Currently Sanguinetti is serving as Chairman at Adapt-IP, but given his long and distinguished history with EDA, he agreed to opine this week on Grand Challenges in EDA. In the following conversation, he offers two Grand Challenges in EDA and two in Security, the latter being an issue of rapidly growing concern worldwide.

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Siemens snags Mentor: Cartel canceled, Gary Smith vindicated

Thursday, March 30th, 2017

 


Today is the day some EDA purists thought would never happen
: The disassembling of an industry status quo that’s been in place for over 20 years

As of today, Mentor Graphics has been sold and is fully owned by Siemens. Now Mentor’s arc of history will be decided by folks not residing in the green forests and hills of northern Oregon, and the Big Three cartel is no more. A cartel which has slowly consolidated the playing field over time until nary a startup can be seen.

The power vested in the Big Three EDA companies has grown steadily and inexorably over these years, as has their market dominance. Examination of recent numbers provided by the ESD Alliance Market Statistics Service indicates that today, in excess of 85-percent of the revenue earned in the EDA industry can be attributed to the combination of Synopsys, Cadence, and Mentor Graphics.

These three companies, their leadership, sales prowess, and increasing control of the conversation and technical direction in the industry has made for a powerful cartel. But again, that cartel is no more and the crystal ball predicting future dynamics within the EDA industry has gone dark.

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ESDA’s Big Four Panel: 20 Questions that won’t be asked

Thursday, March 23rd, 2017

 


Something historic and poignant
is taking place on Thursday, April 6th, that should be of interest to absolutely everyone in the EDA and IP communities. The four most powerful men in these two industries will be on stage for an ESD Alliance panel discussion led by Semiconductor Engineering’s Ed Sperling.

The four panelists include Synopsys Chairman & CEO Aart de Geus, Cadence President & CEO Lip-Bu Tan, Mentor Graphics Chairman & CEO Wally Rhines, and ARM CEO Simon Segars.

The April 6th event will be historic because these Big Four unequivocally define EDA and IP – just as Stanford, Huntington, Hopkins, and Crocker defined Railroads in the West – and it’ll be poignant because you’ll never see them together again. Too many changes ahead.

Of course, the ESDA panel will also be whimsical: You’ll know no more about these CEOs and their companies at the end of the evening than you knew when you first arrived. That doesn’t mean the evening won’t be entertaining.

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Job Openings: Can EDA Predict the Future

Thursday, March 9th, 2017

 


This is a simple post with just two messages
. First, EDA is hiring. All over the globe. Mentor Graphics lists over 200 openings, Cadence has almost 300 openings, and Synopsys has a staggering 900+ openings worldwide.

Of course, EDACafe’s own Mark Gilbert could have told you this. It wasn’t necessary to scour the websites of the Big Three in EDA to learn about the many jobs currently available in the industry, most for software developers, not surprisingly.

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Synopsys: Is 40 the new 20?

Thursday, January 19th, 2017


Synopsys is undergoing a massive reset.
Where not so long ago, it self-identified as the largest EDA company in the world, other words are now used to describe the enterprise: “Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.”

As compelling as that description may be, some observers are questioning whether the marked differences between maintaining expertise in chip design, verification, IP, and IP integration versus maintaining expertise in software integrity are too wide to make for easy co-habitation under one corporate roof.

Some would say putting EDA and chip design together with software security is not a good recipe for the long-term success of the company. But are these critics correct?

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Kaufman Award Dinner: Why you should Attend

Thursday, January 5th, 2017

 


IEEE’s CEDA and the ESD Alliance
– with help from their friends at PDF Solutions, Cadence, Mentor, Synopsys and ACM SIGDA – will host a dinner on Thursday, January 26th, in honor of the 2016 Phil Kaufman Award recipient: Dr. Andrzej Strojwas, Keithley Professor of ECE at Carnegie Mellon and long-time CTO at PDF Solutions.

Unfortunately, the last several Kaufman Award dinners were such over-the-top events – the 2014 event in honor of Dr. Lucio Lanza awash in glamour and luminaries, and the 2015 event in honor of Dr. Walden Rhines replete with zany zeitgeist and a roast from Intel-legend Craig Barrett unparalleled in the annals of EDA history.

The organizers of this year’s event may, therefore, find it impossible to craft something anywhere close to the previous two dinners, if the metrics of energy and frenetic glad-handing are the only ones of importance.

Of course, these are not the only two metrics of importance and nothing is ever impossible in EDA or IP, so do not despair.

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CEDA’s DAFW 2016: Romance Novel v. Non-Fiction v. Classic Rock

Wednesday, October 26th, 2016

 


Last week on Friday and Saturday
, the IEEE Council on EDA hosted a 2-day workshop to discuss the future of design automation. Mentor Graphics provided the venue – a large conference room in their Fremont/Silicon Valley campus – and workshop leaders, UCSD Prof. Andrew Kahng, UCSD Prof. Farinaz Koushanfa, and Intel alum/CEDA President Shishpal Rawat provided the welcome.

Over the two days, a group of 50+ attendees – representing a wide cross-section of academics and industry experts – launched into conversations that were lively, energized, at times contentious, and completely engrossing. Put simply, there was no better place on the face of the globe on October 21st and 22nd where tech junkies were more intellectually challenged and entertained than at the Design Automation Futures Workshop in Fremont.

What made the workshop so compelling? For this, their inaugural DAFW, CEDA chose to address neuromorphic computing – the ultimate hotness related to machine learning, with a lot of promise for future applications. It doesn’t get any more design futures, or futuristic, than this.

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Calling Srivastava, Madhavan, Rowen, Kranen: ESDA needs you on November 1st

Thursday, October 13th, 2016

 


Congrats to the ESD Alliance for continuing
to attend to myriad legal issues that surround the business of technology. On Tuesday, November 1st, the organization is hosting an evening panel on the Cadence campus entitled “Legal Steps to Maximize Your Exit Value.”

Vital topics slated for discussion include setting the proper price for intangible assets – in-house IP, strategic partnerships, and good will – and more prosaic issues such as the appropriate legal structures and pre-deal tax planning needed to help facilitate the acquisition. Most importantly, panel organizers are also promising you’ll learn “how to avoid giving it all back to your buyer later”.

Which is where our EDA M&A Hall of Fame comes in. There’s just no way this ESD Alliance panel can carry any weight with a battle-hardened EDA audience without the likes of Sanjay Srivastava, Rajeev Madhavan, Chris Rowen, and Kathryn Kranen sitting up at the front of the room.

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SNPS & OneSpin: Saving for Rainy Day not always Best

Thursday, August 18th, 2016

 


As of August 17th, when they posted financial results for Q3_2016
, Synopsys is reporting somewhere in the neighborhood of $1 billion in cash and cash equivalents. As prudent as it may be to save for a rainy day, here’s something a bit more creative the company could do with a portion of that cash: Buy OneSpin.

Why? Because OneSpin offers something that Synopsys doesn’t have – a market-leading position in formal verification. OneSpin would bring that to Synopsys, along with a strong, well-established track record and proven customer engagements across European, North American and Asian markets.

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DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL



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