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Posts Tagged ‘SiSoft’

DesignCon: From Pragmatic to Dramatic, it’s all there

Thursday, January 26th, 2017

 


Next week, DesignCon 2017 will be underway
at the Santa Clara Convention Center. As always, the program will include a lot of practical advice across a variety of design silos: Analog & mixed-signal modeling and design; modeling and analysis of interconnects.; PCB design, simulation, and fabrication; chip/package design and signal integrity considerations; EM interference; and various aspects of high-speed design.

DesignCon clearly continues to provide a learning venue for working engineers who deal with real-world problems, and again this year there will also be a lively exhibit hall.

Featured among the 185 exhibitors will be multiple companies offering tools for design – Cadence, Altium, Ansys, SiSoft, Mentor Graphics, Applied Simulation, EMA, DipTrace, Polar Instruments, SPISim, Valydate, XJTAG, and SpeedIC, among them.

Also exhibiting this year at DesignCon will be our own EDACafe.

Sanjay Gangal, President of IBSystems, and his team will be in Booth #1349 where they will be recording video interviews.

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SI: What comes after CDNS acquires Sigrity?

Thursday, July 5th, 2012

 

The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?

Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …

… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.

This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?

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Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



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