Posts Tagged ‘Samsung’
Thursday, May 5th, 2016
Luckily I arrived late to EDPS in Monterey on Friday, April 22, because I did not hear the introduction of the first keynote speaker or hear his name. A good thing, as it turns out. The speaker was a technologist who doesn’t embrace technology when it’s used as a tool for intrusions into our lives. He’s concerned about how our private facts have become part of the public fabric, accessible to anyone who knows how to navigate the Cloud.
And so, in the spirit of Life imitating Art, I’m not going to list his name here. That detail is fully available on the EDPS website, but it will not be articulated here. What will be articulated here, however, is the audience reaction to the Keynoter’s comments. The audience became part of the presentation, with the keynote address quickly morphing into a round table discussion, a group therapy session for technology whiz-kids who worry about the increasingly public nature of our private lives in this digital, always-connected era.
Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run
wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
Tuesday, June 10th, 2014
UMass Amherst’s Sandip Kundu moderated a Thursday afternoon panel at DAC entitled, ‘Designing on Advanced Process Nodes: How many re-spins should you plan for?’
In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.
Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”
It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.
Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.
Thursday, January 23rd, 2014
Long, long ago in a galaxy far, far away the EDA Empire began and quickly coalesced into several big players and a band of plucky startups constantly attempting to compete and stay viable.
Back in that halcyon era, Rick Carlson and Dave Millman decided to get those startups to pull as one, to try to keep the industry open and progressing, to protect the EDA industry as a place where new ideas could see the light of day and offerings from small companies could compete on a level playing field against those from the big players.
To do that, Rick and Dave came up with the idea for a consortium of Independent Design Automation Companies, IDAC, and put out the word to like-minded colleagues that this new group would benefit everybody. Creating IDAC proved more difficult than they had hoped, so letting pragmatism rule the day they approached Joe Costello for help, then CEO of Cadence, even though that meant working with one of the ‘big guys’ and hence, EDAC came to fruition.
To hear the rest of the story per Rick, recounted in a phone call in December, click here.
To hear the story recounted by Joe Costello, read below. I spoke with both Joe and Rick together on a conference call in mid-January.
Revolution from within …
Joe began: “Rick told me he’s concerned that in his recent conversation with you about the history of EDAC, he may have sounded too harsh. I said that’s not possible, because the truth about the industry is quite harsh. Just thinking about it makes my blood boil.
Thursday, September 5th, 2013
Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.
In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.
Fully-depleted SOI …
Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.
“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.
Tuesday, June 4th, 2013
The only thing most people remember about Tuesdays at DAC are the parties. You’re a success if you attended at least two, less than a success if you only attended one, and guaranteed immortality if you attended more than three.
Of course, other things happen on Tuesdays at DAC – early morning breakfasts where sincere technologists present and/or opine about somber challenges facing the industry, the plenary session, presentation of multiple awards, pavilion panels, mid-day luncheons, afternoon sessions, posters, and many, many hours logged in by booth staff talking and talking and talking to customers, potential customers, and general industry hangers-on looking for free give-aways.
Thursday, March 14th, 2013
From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.
Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.
Tuesday, January 22nd, 2013
Several weeks into his new gig at Carbon Design Systems, it was a pleasure to speak by phone with Hal Conklin, VP of Sales and Marketing at the company. Conversationally, it was a bit of a random walk.
WWJD: Prior to joining Carbon, what were you doing?
Hal Conklin: I was doing enterprise software development for the government. I enjoyed the work, but not working for the government. I did that for 3 years and was quite successful, but it wasn’t something I wanted to do long term.
WWJD: So what inspired you to join Carbon?
Hal Conklin: I’ve been in EDA for quite a while and know how important it is to be with a company that has a product and customers who renew [their licenses]. Carbon is particularly important today with the changes that are coming in virtual prototyping. So given all the good stuff I’ve been seeing, I joined the company.
Wednesday, September 5th, 2012
There are thousands of companies based in Silicon Valley, but not all of them focus on the long-term play. Valin Corp. does have that focus, however, intentionally balancing their product portfolio across a range of industries, and investing in their employees with equal intensity.
Company President & CEO Joe Nettemeyer told me in a recent phone call that this strategy has allowed Valin to grow non-stop over the last half-decade: “We’ve achieved growth through a combination of internal development and acquisition, averaging 20-percent growth or more, per year, over the last 5 years, even in spite of a slight hiccup in 2009. We like to invest in industries that are counter-cyclical to each other. When there’s a slow-down in one area, we can cover the slack with revenue in another.
“We’re an infrastructure company working in the wafer-fab-equipment end of the semiconductor industry, designing and building system solutions for companies around the world that make semiconductor-based products. We just completed a project with AKT that makes equipment for large flat-screen panels to retrofit 30 systems for Samsung.
“We’ve also expanded our capabilities in other industries over the years, particularly as a strategic global distributor for Applied Materials. We’re recognized as one of the top 40 industrial distributors in the nation based on our sales revenue, and have just been recognized as one of INC Magazine’s 500/5000 fastest growing companies in America.
Sunday, May 13th, 2012
If you do nothing else on Wednesday, June 6th, at the Design Automation Conference be sure to attend the second of the two keynotes.
Intel’s Brad Heaney will be talking about “designing a 22nm Intel Architecture Multi-CPU and CPU.” It’s got well over a billion transistors and would have only been the stuff of Sci-Fi dreams a brief 15 or 20 years ago.
After that, just like on Terrible Tuesday, you’ve got a wicked wheelbarrow full of different ways you could go, starting with the User Track. The Wednesday line-up in this well-received recent addition to the DAC schedule includes:
* Packaging & Automatic P&R, with speakers from Mentor Graphics, Samsung, and Intel
* Keynoter Q&A, with the morning’s IBM & Intel speakers fielding questions from the crowd
* Practical Formal Methods, with speakers from IBM, Oski, and Intel
If your interests, however, reside with the young more than the mega-organizations in the EDA ecosystem, Wednesday is your day to visit the ACM Sigda University Booth in the Exhibition Hall, where the “new EDA tools, EDA tools applications, design projects, and instructional materials” will be your guide to the future minds of this industry.