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Posts Tagged ‘Paul McLellan’

EDPS: Conversation overlooking the sea

Thursday, April 3rd, 2014

 

There are lots of clever ways to tell you why it’s worth your while to attend EDPS in Monterey on April 17th and 18th. It’s less noisy than DAC, less vendor-specific than CDNLive, SNUG or U2U; less crowded than ISSCC; has fewer presentations than DVCon; and boasts no co-located events to confuse your schedule like at ISQED. But that doesn’t tell you why EDPS is worthwhile. It’s the list of speakers and the setting that should convince you to carve out some time on that Thursday and Friday to run down to Monterey – a scenic hour’s drive from Silicon Valley – to attend the 21st annual Electronic Design Process Symposium.

On Thursday, Wally Rhines is giving the keynote after dinner; during the day, Gary Smith’s moderating a session on design flow challenges that includes Frank Schirrmeister, John Swan, Gene Matter, Jim Kenney, and Naresh Sehgal; Sehgal’s leading a session on pre-silicon software development platforms that includes Camille Kokozaki, Shantanu Ganguly, Kumaraswamy Namburu, Schirrmeister, and Vicki Mitchell; Herb Reiter’s moderating a session on FinFETs, 3D-ICs, and FDSOI, that includes Jamil Kawa and Paul McLellan; and the kick-off keynote on Thursday morning will be given by Intel’s Chris Lawless talking about pre-silicon platforms for software development.

On Friday, Dan Nenni’s leading a whole day on IP that includes Martin Lund, Patrick Soheili, Warren Savage, Kurt Shuler, Lluis Paris, Carey Robertson, and Bernard Murphy. Finally, Aparna Dey is General Chair for EDPS. All together, that’s 24 people and a robust ecosystem of knowledge and experience comprising this year’s EDPS program.

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DAC 2012: Wicked Wednesday in San Francisco

Sunday, May 13th, 2012

 

DAC looms!

If you do nothing else on Wednesday, June 6th, at the Design Automation Conference be sure to attend the second of the two keynotes.

Intel’s Brad Heaney will be talking about “designing a 22nm Intel Architecture Multi-CPU and CPU.” It’s got well over a billion transistors and would have only been the stuff of Sci-Fi dreams a brief 15 or 20 years ago.

After that, just like on Terrible Tuesday, you’ve got a wicked wheelbarrow full of different ways you could go, starting with the User Track. The Wednesday line-up in this well-received recent addition to the DAC schedule includes:

* Packaging & Automatic P&R, with speakers from Mentor Graphics, Samsung, and Intel
* Keynoter Q&A, with the morning’s IBM & Intel speakers fielding questions from the crowd
* Practical Formal Methods, with speakers from IBM, Oski, and Intel

If your interests, however, reside with the young more than the mega-organizations in the EDA ecosystem, Wednesday is your day to visit the ACM Sigda University Booth in the Exhibition Hall, where the “new EDA tools, EDA tools applications, design projects, and instructional materials” will be your guide to the future minds of this industry.

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Pop Quiz: The Standards Game

Friday, February 17th, 2012

 

Here’s your February Pop Quiz.

******************

1 – DVCon 2012 starts on February 27th. The conference was first held in _____.

a) 1989
b) 1995
c) 1998
d) 2003

2 – The IEEE Standards Association [IEEE-SA] oversees approximately _____ standards and _____ standards under development.

a) 500, 900
b) 800, 600
c) 900, 500
d) 700, 900

3 - The IEEE Standard associated with VHDL is _____.

a) IEEE Std 1064
b) IEEE Std 1076
c) IEEE Std 1164
d) IEEE Std 1176

4 – Accellera merged with _____ in 2011.

a) VSIA
b) OSCI
c) OCP-IP
d) OVI

5 – DVCon is managed by MP Associates, the same group that manages _____.

a) ICCAD
b) DesignCon
c) Semicon
d) ISQED

6 – The 2007 General Chair of DVCon was _____.

a) Tom Fitzpatrick
b) Stephen Bailey
c) Shankar Hemmady
d) Gabe Moretti

7 – SystemVerilog was donated to Accellera in _____.

a) 2000
b) 2001
c) 2002
d) 2003

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