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Posts Tagged ‘Mentor Graphics’

Sanjiv Kaul: Calypto and HLS to seize the day

Thursday, May 16th, 2013

 

Privately-held Calypto is on quite a clip these days, with developments at the company being closely followed by the press. That’s not completely surprising given that a new CEO came on board earlier this year, Sanjiv Kaul, and a new VP of Applications Engineering was named just this week, Thomas Bollaert being promoted into that role. I had a chance to speak with CEO Kaul recently. Following is a snapshot of that conversation.

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DAC 2013: a Taste of Texas

Thursday, April 25th, 2013

 

Surely EDA is a serious-minded industry, particularly when it comes to ramping up for the annual Design Automation Conference where it’s all work and no play. Nonetheless, sometimes it just has to be okay to relax a little and hence the spirit of this blog.

Thanks to native Texans Sonia Harrison and Kathryn Kranen of Mentor Graphics and Jasper Design Automation, respectively, as well as my vintage copy of the Tasting Bee cookbook from the University of Texas San Antonio Health Science Center, herein are included some mighty fine recipes – Calabazita, Migas, Golden Potato Casserole, Texas Chili, and a refreshing chaser – to try out and enjoy over the next few weeks as the 50th DAC draws near and the Lone Star State beckons.

Bon Appetit, y’all!

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EDPS 2013: surf, sand, serenity, semiconductors

Thursday, April 4th, 2013

 

Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.

Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.

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Rhines: roadmaps built on EDAC and Gary Smith

Monday, April 1st, 2013

 

EDAC’s Market Statistics Service today announced Q4 2012 revenue and happily reported a 4.6 percent increase, year over year, compared with Q4 2011. Per the press release: “Sequential EDA revenue for Q4 2012 increased 9.8 percent compared to Q3 2012, while the four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 6.7 percent.”

Mentor Graphics Chairman & CEO Wally Rhines confirmed the industry’s good news in a phone call to discuss the MSS numbers. “A 6.7 percent increase is good and continues a reasonable mid-single digit trend in growth rate,” he said.

“Also, growth in the industry was pretty uniform around the world, except for Japan which showed a little weakness. Surprisingly, Europe was the strongest, while from a product category point of view, things remain strong across the front end, particularly in printed circuit boards. And interestingly, the survey data showed that the IP sold by EDA companies was stronger [in the market] than that sold by IP companies.”

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EDAC CEO Panel: Practically perfection

Thursday, March 14th, 2013

 

From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.

Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.

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DVCon 2013: There is such a thing as a free lunch!

Thursday, February 21st, 2013

 

You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.

If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.

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Rhines: Q3 2012 EDAC stats drive optimism

Thursday, January 10th, 2013

 

EDA veteran Dr. Walden Rhines, Mentor Graphics CEO & Board Chairman, is one of the keenest and most optimistic observers of the industry. We spoke this week about the recent EDAC Market Statistics Service [MSS] numbers for Q3 2012.

Per Rhines: “EDA is growing at a rate almost a percentage greater than a year ago and most strongly in the Asia Pacific region, while also growing in other regions as well. [Only] Japan is not growing.”

He said there is growth in all product areas, but the “biggest growth is in the areas of new methodologies. ESL is very strong, and interestingly on the PCB side [growth was seen in] analysis tools such as signal integrity. But packaging is also growing, strongly consistent [with growth] in the new methodologies.”

Rhines also noted that CAE strength was largely influenced by growth in hardware-assisted verification (a.k.a. emulation), as well as the already mentioned ESL design.

“There’s actually healthy growth in everything,” he said, “except design verification and physical design and verification, which are both a little bit down. That’s largely caused by place-and-route, although detailed layout continues to be strong. [To be specific], the big category in physical design and verification is fine, and yield enhancement is fine, but standard place-and-route is weaker. If I had to come up with a reason, everything tends to have its ups and downs, so [in the long run] even place-and-route is still a good growth area.”

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HAPS-70: a distinguished provenance

Monday, November 12th, 2012

 

If you’re an IP developer, or somebody who develops SoCs where blocks of IP land, Synopsys is announcing a product today that will be of interest: the HAPS-70 Series. It’s a prototyping system with a distinguished provenance that runs your ASIC-targeted design on FPGAs for validation prior to tape-out.

HAPS-70 started its journey to your work place way back in 1987 when Sweden-based HARDI Electronics was founded. The folks at HARDI developed the original HAPS prototyping system, which became part of Synplicity’s arsenal in 2007 when HARDI was acquired by SYNP, and the product was relaunched as HAPS-54.

Gary Meyers was President and CEO of Synplicity at the time, and was quoted: “This is a major strategic move for Synplicity. We will be able to immediately leverage our existing ASIC verification products (Certify, Synplify Premier, Identify, and Identify Pro) by selling them together with the HARDI ASIC prototyping boards.”

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Ausdia: Sanjay Lall joins the board

Thursday, November 8th, 2012

 

It might be the impression of late that all EDA-startup roads lead to Synopsys, but that would be incorrect. Small, privately-held companies continue to make their way in the industry, independent and productive.

Ausdia, based in Silicon Valley, has been underway since 2006 developing tools for timing constraint verification and management. Today the company announced a new board member, Sanjay Lall. Per the press release, Lall has 20+ years of experience in the EDA and semiconductors, “an expert in operations, marketing, fund raising and sales.”

He is also Chairman and Managing Partner at Cronox Group, on the Board of Advisors at Verdigirs Technologies, and a Director at Mobi-holdings. Previously, Lall was VP of Sales at Extreme DA, and “influential in the company’s acquisition by Synopsys in 2011.”

All EDA-startup roads may not lead to Synopsys, but not surprisingly the CVs of most seasoned EDA veterans do lead to Synopsys, and/or to Cadence and/or Mentor Graphics.

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ProPlus: DFY solution unveiled

Thursday, November 1st, 2012

 

The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.

In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.

Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.

“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.

“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”

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Verific: SystemVerilog & VHDL Parsers



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