Posts Tagged ‘Mentor Graphics’
Thursday, March 14th, 2013
From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.
Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.
Thursday, February 21st, 2013
You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.
If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.
Thursday, January 10th, 2013
EDA veteran Dr. Walden Rhines, Mentor Graphics CEO & Board Chairman, is one of the keenest and most optimistic observers of the industry. We spoke this week about the recent EDAC Market Statistics Service [MSS] numbers for Q3 2012.
Per Rhines: “EDA is growing at a rate almost a percentage greater than a year ago and most strongly in the Asia Pacific region, while also growing in other regions as well. [Only] Japan is not growing.”
He said there is growth in all product areas, but the “biggest growth is in the areas of new methodologies. ESL is very strong, and interestingly on the PCB side [growth was seen in] analysis tools such as signal integrity. But packaging is also growing, strongly consistent [with growth] in the new methodologies.”
Rhines also noted that CAE strength was largely influenced by growth in hardware-assisted verification (a.k.a. emulation), as well as the already mentioned ESL design.
“There’s actually healthy growth in everything,” he said, “except design verification and physical design and verification, which are both a little bit down. That’s largely caused by place-and-route, although detailed layout continues to be strong. [To be specific], the big category in physical design and verification is fine, and yield enhancement is fine, but standard place-and-route is weaker. If I had to come up with a reason, everything tends to have its ups and downs, so [in the long run] even place-and-route is still a good growth area.”
Monday, November 12th, 2012
If you’re an IP developer, or somebody who develops SoCs where blocks of IP land, Synopsys is announcing a product today that will be of interest: the HAPS-70 Series. It’s a prototyping system with a distinguished provenance that runs your ASIC-targeted design on FPGAs for validation prior to tape-out.
HAPS-70 started its journey to your work place way back in 1987 when Sweden-based HARDI Electronics was founded. The folks at HARDI developed the original HAPS prototyping system, which became part of Synplicity’s arsenal in 2007 when HARDI was acquired by SYNP, and the product was relaunched as HAPS-54.
Gary Meyers was President and CEO of Synplicity at the time, and was quoted: “This is a major strategic move for Synplicity. We will be able to immediately leverage our existing ASIC verification products (Certify, Synplify Premier, Identify, and Identify Pro) by selling them together with the HARDI ASIC prototyping boards.”
Thursday, November 8th, 2012
It might be the impression of late that all EDA-startup roads lead to Synopsys, but that would be incorrect. Small, privately-held companies continue to make their way in the industry, independent and productive.
Ausdia, based in Silicon Valley, has been underway since 2006 developing tools for timing constraint verification and management. Today the company announced a new board member, Sanjay Lall. Per the press release, Lall has 20+ years of experience in the EDA and semiconductors, “an expert in operations, marketing, fund raising and sales.”
He is also Chairman and Managing Partner at Cronox Group, on the Board of Advisors at Verdigirs Technologies, and a Director at Mobi-holdings. Previously, Lall was VP of Sales at Extreme DA, and “influential in the company’s acquisition by Synopsys in 2011.”
All EDA-startup roads may not lead to Synopsys, but not surprisingly the CVs of most seasoned EDA veterans do lead to Synopsys, and/or to Cadence and/or Mentor Graphics.
Thursday, November 1st, 2012
The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.
In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.
Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.
“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.
“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”
Thursday, October 25th, 2012
Montreal is not a place that normally comes to mind when you think of EDA. Space Codesign Systems, however, is on a fast track to change that in a classically Canadian way – calm, cool, and collected.
When I spoke with General Manager Dr. Gary Dare on a beautiful afternoon in Southern France at SAME Forum in early October, he explained how the company started in Canada, and the road map they have set out for themselves: “We’re an EDA company, an EDA startup, and we are definitely based in Montreal. If you doubt that EDA has a place in Canada, we will soon convince you otherwise.
“Space Codesign comes from the acronym, SystemC Partition of ACE, which was the 2004 research project at the Ecole Polytechnique [University of Montreal] that our technology is based on. In 2008, Professor Guy Bois and various graduate students associated with the project decided to do a spin-out, and in 2010 Space Codesign Systems went into operation.”
He laughed and added, “Our company has nothing to do with space, however. But it has everything to do with hardware/software co-design – doing it simultaneously, rather than the usual way of ESL hardware design followed by software design. The audience we are targeting is the systems architects who are looking at the algorithmic level and need a route to design exploration and implementation. Our tools give them that route.
Tuesday, October 2nd, 2012
It’s not often that the rumor hits the fan that Synopsys is buying EVE, it’s not often that you’re standing in a cocktail party at a tech conference in the South of France, and it’s not often that these two events happen simultaneously.
When the Synopsys/EVE rumor swept through the cocktail party in Sophia Antipolis on this first evening of the SAME Forum, not surprisingly a lot of people had opinions. This is not just a tech conference, after all, it’s a microelectronics conference with an emphasis on design; EDA is at the center of the conversation.
This is also Europe and at the moment EVE, headquartered in France, is the darling of the EDA ecosystem on the Continent. The company is doing very well, is felt to be holding its own in a series of lawsuits with Mentor Graphics, and is widely admired overall. Needless to say, the reaction over cocktails that EVE may go the way of SpringSoft and Magma was not one of jubilation. Just the opposite, in fact.
Thursday, August 23rd, 2012
There are at least 4 ways to learn about Patent Law:
1) Go to law school.
2) Follow the ginormously expensive shoot-out between Samsung & Apple.
3) Read my articles on Patent Law.
* Patent Law 101: Patent Prosecution
* Patent Law 102: Patent Litigation
4) Read recent Press Releases out of EDA.
* Mentor Graphics announces filing of suit against EVE for patent infringement
* EVE Will Continue to Defend Itself Against Mentor Graphics’ Patent Infringement Suits
* Sidense wins patent infringement case against Kilopass
* Kilopass Plans to Appeal the Summary Judgment Ruling in its Patent Infringement Case Against Sidense
Clearly options 1 & 2 would take way too much time, so let’s go with a combo of options 3 and 4: First revisit several highlights of my articles on Patent Law, and then review the recent press releases regarding EDA-related litigations.
Thursday, August 9th, 2012
Ali Iranmanesh is a busy man. He continues to head up the Silicon Valley Institute of Technology, the school he founded in 1997, and continues to lead ISQED, the conference he founded in 1999. Now he is also leading ASQED, the Asia-based spin-off of ISQED Iranmanesh founded in Malaysia.
I caught up with Ali in early August by phone. He was in Silicon Valley and had just returned from ASQED 2012 in Penang, Malaysia.
WWJD: What prompted you to start ASQED?
Ali Iranmanesh: It was a natural extension of ISQED, which I started 14 years ago. I decided to keep ISQED in Silicon Valley, and to create other conferences for different regions.
WWJD: Remind me how many ASQED’s have taken place.
Ali Iranmanesh: This is our fourth year, with the conference alternating between Kuala Lumpur and Penang in Malaysia. Our next event is scheduled for August 26th to 28th in Penang.
WWJD: Malaysia seems an unusual destination for a conference on design.
Ali Iranmanesh: Historically, there has been a lot of manufacturing in Malaysia, but not so much design. I’ve been working with the several government entities there, helping them to move up the value chain through training, and was able to implement the conference as part of that process. Now for the past few years, there has been design going on in Malaysia – the conference has done a great job helping with that.