Posts Tagged ‘Mentor Graphics’
Thursday, May 29th, 2014
Like a phoenix rising from too-early reports of a reduced participation in life, the legendary Gary Smith has created a schedule of appearances at the 51st Design Automation Conference in San Francisco that would fell a man half his age. Every time you turn around at Moscone Center next week, or the Intercontinental Hotel before that, you’ll be face-to-face with events featuring the Guru Extraordinaire of EDA.
Sunday evening from 5:00 pm to 5:30 pm, Gary will yet again ring the opening bell at DAC, this year in Ballroom A of the Intercontinental Hotel across the street from Moscone. I’m putting good money on a bet that Gary will be on stage there in his best Tropical Whites, accompanied by slides, predictions, and previews of the Next Epoch in EDA and his Pavilion Panel the next day.
Thursday, May 1st, 2014
A friend likes to spend hours on Sundays reading the New York Times cover to cover. Pointing to an article from last weekend’s edition, he exclaimed, “This Putin guy is a real piece of work! He’s a total dictator and worse, thinks he can win the world war he’s about to unleash!”
“Stay calm and carry on,” I said soothingly. “It’s a global economy these days and he will succumb to the pressures of maintaining a steady environment for international trade.”
“Yeah?” the friend scoffed. “And you call yourself a student of history? You don’t think there was a global economy in 1939?”
“Look,” I said. “Seriously. The EDA industry is in Moscow. Do you think they’d be playing in an environment that’s spiraling out of control?”
“Yeah?” he retorted. “The world, starting with Putin, doesn’t care about your precious EDA. And besides, who says EDA’s in Moscow?”
Thursday, April 24th, 2014
Talking to ProPlus Design Solutions requires a long view of history over at least the last 20 years in EDA. In 1993, BTA, an EDA company focused on device model extraction and SPICE simulation, was founded with U.C. Berkeley’s Dr. Chenming Hu as Chairman of the Board. In 1999, BTA merged with Ultima, and became Celestry in 2001.
Finally, in 2003, the combined companies were acquired by Cadence Design Systems. Then in 2007, a new company called ProPlus was spun out of Cadence to support the original BSIMProPlus device modeling platform with roots going back to BTA/Celestry.
Current ProPlus CTO Bruce McGaughy earned his PhD at Cal with Chenming Hu as his advisor, served at both BTA and Celestry, and worked at Cadence, before joining ProPlus 6 years ago. I had a chance to talk with Dr. McGaughy in person last month in Silicon Valley. Our conversation covered a range of topics.
Monday, April 21st, 2014
In the moments prior to Cadence’s quarterly earnings call this afternoon, the company released news of the acquisition of Jasper Design Automation for $170 million, less $24 million in cash, and a small tremor rippled out across the EDA Nation.
Paraphrasing Cadence CEO Lip-Bu Tan in the early minutes of his 5pm ET earnings call: We are very pleased to announce a definitive agreement to acquire Jasper Design Automation. This will help us to further meet our customers’ needs for more advanced verification solutions, particularly today as verification now represents 70% of the cost of SoC development. Together, Cadence and Jasper can move forward, offering the strong formal verification solutions leading customers need. In addition, Cadence is also very pleased to be bringing on board the strong team at Jasper, a team with excellent real-world experience.
All good stuff, yes? So why any tremors in our beloved little EDA Nation?
Thursday, April 17th, 2014
Overlooking the inky calm of Monterey Bay, the lights of tethered boats in the marina reflecting in the shimmering waters below, Wally Rhines delivered a mesmerizing after-dinner keynote on Thursday night, a gift to an intimate group of EDPS attendees assembled in the low-slung Monterey Bay Yacht Club adjacent to the municipal pier.
It was textbook Rhines: a detailed re-telling of the last 50 years of the semiconductor industry with a log-log analysis of the validity of various versions of Moore’s Law, a dizzying display of data on shrinking feature sizes, and an adamant admonition that the law is, in fact, an economic learning curve with applicability that extends beyond the narrow confines of electronics.
From there, Rhines talked at length about what constitutes a process node, the gulf between Engineering’s obsession with gate length and Marketing’s obsession with world domination, and how reality got so out of whack with message that in recent years the ITRS had to step in and put an end to a war of claim versus counter-claim. Nonetheless, per Rhines, one company’s 16nm today is another company’s 14nm, as the murky physics behind the labels obfuscates to confuse the customer and confound the competition.
But the real core of Rhines’ talk was still to come: He addressed the issue of margins, head-on, across the entire spectrum of the semiconductor food chain, one micro-segment at a time. To do this to completion required many more charts, extensive additional analysis, and a lot more time. Yet, even as the hands of the clock over the bar inched well past 9 pm, no one in the room budged, yawned, or dozed – so complete was Rhines’ mastery of the material and command of the context. It was brilliant.
Friday, March 21st, 2014
It’s Friday afternoon and spring is busting out all over, so why would anyone want to sit on a conference call and talk about EDA? Well, if you were Ravi Subramanian, President and CEO of Berkeley Design Automation, you would. The company he leads has just been sold to Mentor Graphics and today’s his day to celebrate the feat with the press.
I spoke with Ravi for 20 minutes this afternoon and remembered straightaway why he is the real thing. Well spoken, fully informed, and completely disciplined in his presentation, still his extreme delight with the acquisition was in full view as he patiently fielded my questions.
Thursday, March 13th, 2014
The following conversation with Joe Sawicki, VP/GM of Mentor Graphics’ Design-to-Silicon Division, looks at the complexities of deciding if and when a company should move down to the next process node. The interview was inspired by an upcoming panel at DAC, Designing on advanced process nodes: How many respins should you plan for?
Sawicki is an acknowledged expert in design and manufacturing, and “responsible for Mentor’s design-to-silicon products, including the Calibre physical verification and DFM platform, and the Tessent design-for-test product line.” I spoke to him by phone this week while he was traveling in Japan on business.
Wednesday, March 12th, 2014
In the spirit of full disclosure, Cadence paid for lunch yesterday for the Press Corps attending CDNLive 2014. We had a scrumptious gourmet meal at Tosca in the lobby of the Hyatt Regency before returning to the Santa Clara Convention Center next door to have an hour-long “one-on-one” with Cadence CEO Lip-Bu Tan. In truth, it was actually an hour-long “twenty-on-one” with CEO Tan, because all of the usual suspects EDA Press Corps was in the room throwing softball lobbing questions at Tan.
Over the course of the hour, we learned that CEO Tan has a host of different investment partners – sorry, didn’t write down the names – involved in his various VC-funded ventures that span everything from GoPro [the trendy wearable camera enterprise out of Half Moon Bay] to a fabless startup that he said can tape-out a design at 16 nanometers for a scant $15 million, rather than the usual $150 million being lamented today in the global press. [In fact, Tan mentioned so many ventures he’s involved with, it begs the question: How does he have time to run Cadence?]
We learned that CEO Tan is very excited about all of the technologies involved in the semiconductor design/supply chain, that he believes it’s a great time to be a player in the industry, and that Cadence is innovating rapidly on multiple fronts simultaneously. And if/whenever Tan senses that they’re slowing down in any particular area, he pushes Cadence Engineering to move forward even faster.
Thursday, March 6th, 2014
Oh my gosh: If you arrived at DVCon 2014 at 10:45 am on Tuesday this week, you’d have wondered if you’d wandered into the wrong conference. What happened to sedate, dignified DVCon? Standing at the registration desk on the first floor of the DoubleTree Hotel in San Jose, the volume of noise and conviviality sweeping down the staircase from the upstairs mezzanine was unprecedented. What was going on up there? The DVCon morning poster session, awash in company reps and their ideas, and engineers anxious to engage with both.
When I got to the top of the staircase, I took a moment before plunging into the crowd, amazed at the vitality and the numbers of people hobnobbing among the posters. It wasn’t surprising to learn later in the day from DVCon General Chair Stan Krolikoski that over a thousand people – attendees and exhibitors combined – were at this year’s conference. Clearly, DVCon is enjoying an extraordinary renaissance, so much so that DVCon Europe will be debuting this October in Munich, with DVCon India, DVCon China, and DVCon Japan now in the planning stages. Like I said, omg.
Thursday, February 13th, 2014
If ever there was a year when you thought to attend DVCon, this should be it, according to a recent phone call with Cadence Fellow Stan Krolikoski, serving as General Chair for the second year in a row. That’s because DVCon 2014 will be serving up the D and the V in equal measure, and won’t be skewed towards the V in DVCon as it has been [perhaps] in the past.
Per Stan, “We’ve gotten feedback every year from attendees that they want more emphasis on design. They say they like verification, but they want more design, so last year I gave marching orders to the Technical Program Committee [headed by Paradigm Works’ Ambar Sarkar] that they should add more people on the review committee who represent design.
“It’s actually been a long time in coming. Although last year was the 25th anniversary of the conference, 10 years ago the name was changed to DVCon. Prior to that, it was HDLCon and the content reflected that name. When the name was changed to DVCon it was supposed to include both design and verification, but [functional verification emerged as the larger focus].”
That focus meant that those types of experts tended to dominate attendance, according to Stan, but that’s been fixed this year: “We will still have excellent functional verification sessions at DVCon – everything for the beginner through to the guru, it’s all there – but we will also have sessions on low-power design, on analog/mixed signal, and on system-level design, as well as IP integration. We’re clearly moving away from just verification in adding lots of design content to the program that’s of interest to our audience.”