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Posts Tagged ‘Mentor Graphics’

DesignCon: From Pragmatic to Dramatic, it’s all there

Thursday, January 26th, 2017

 


Next week, DesignCon 2017 will be underway
at the Santa Clara Convention Center. As always, the program will include a lot of practical advice across a variety of design silos: Analog & mixed-signal modeling and design; modeling and analysis of interconnects.; PCB design, simulation, and fabrication; chip/package design and signal integrity considerations; EM interference; and various aspects of high-speed design.

DesignCon clearly continues to provide a learning venue for working engineers who deal with real-world problems, and again this year there will also be a lively exhibit hall.

Featured among the 185 exhibitors will be multiple companies offering tools for design – Cadence, Altium, Ansys, SiSoft, Mentor Graphics, Applied Simulation, EMA, DipTrace, Polar Instruments, SPISim, Valydate, XJTAG, and SpeedIC, among them.

Also exhibiting this year at DesignCon will be our own EDACafe.

Sanjay Gangal, President of IBSystems, and his team will be in Booth #1349 where they will be recording video interviews.

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Kaufman Award Dinner: Why you should Attend

Thursday, January 5th, 2017

 


IEEE’s CEDA and the ESD Alliance
– with help from their friends at PDF Solutions, Cadence, Mentor, Synopsys and ACM SIGDA – will host a dinner on Thursday, January 26th, in honor of the 2016 Phil Kaufman Award recipient: Dr. Andrzej Strojwas, Keithley Professor of ECE at Carnegie Mellon and long-time CTO at PDF Solutions.

Unfortunately, the last several Kaufman Award dinners were such over-the-top events – the 2014 event in honor of Dr. Lucio Lanza awash in glamour and luminaries, and the 2015 event in honor of Dr. Walden Rhines replete with zany zeitgeist and a roast from Intel-legend Craig Barrett unparalleled in the annals of EDA history.

The organizers of this year’s event may, therefore, find it impossible to craft something anywhere close to the previous two dinners, if the metrics of energy and frenetic glad-handing are the only ones of importance.

Of course, these are not the only two metrics of importance and nothing is ever impossible in EDA or IP, so do not despair.

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Hurry, Hurry: Brexit triggers SoftBank/ARM, Election triggers Siemens/Mentor

Monday, November 14th, 2016

 


If you were watching Seattle beat New England last night
, and not the news, you missed it: The rumor that Munich-based Siemens would buy Wilsonville-based Mentor Graphics.

This morning, of course, it’s no longer a rumor. The players themselves have announced that the deed is done.

Per the Press Release, “Siemens and Mentor Graphics today announced that they have entered into a merger agreement under which Siemens will acquire Mentor for $37.25 per share in cash, which represents an enterprise value of $4.5 billion.”

Wow, talk about just in the nick of time.

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CEDA’s DAFW 2016: Romance Novel v. Non-Fiction v. Classic Rock

Wednesday, October 26th, 2016

 


Last week on Friday and Saturday
, the IEEE Council on EDA hosted a 2-day workshop to discuss the future of design automation. Mentor Graphics provided the venue – a large conference room in their Fremont/Silicon Valley campus – and workshop leaders, UCSD Prof. Andrew Kahng, UCSD Prof. Farinaz Koushanfa, and Intel alum/CEDA President Shishpal Rawat provided the welcome.

Over the two days, a group of 50+ attendees – representing a wide cross-section of academics and industry experts – launched into conversations that were lively, energized, at times contentious, and completely engrossing. Put simply, there was no better place on the face of the globe on October 21st and 22nd where tech junkies were more intellectually challenged and entertained than at the Design Automation Futures Workshop in Fremont.

What made the workshop so compelling? For this, their inaugural DAFW, CEDA chose to address neuromorphic computing – the ultimate hotness related to machine learning, with a lot of promise for future applications. It doesn’t get any more design futures, or futuristic, than this.

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Morphing Mentor: Haiku haunts Wilsonville

Thursday, October 6th, 2016

 


In July 2008 and with much fanfare
, Cadence declared its intention to purchase Mentor Graphics. The Cadence executive team was so confident the purchase would go through, then-CFO Bill Porter declared during an analysts’ call at the time: This acquisition is going to happen, Mentor needs us. Accept it and move on.

Well, people did move on. By September 2008, Cadence CEO Mike Fister, CFO Porter and the entire executive team had indeed moved on. CDNS Board member Lip-Bu Tan was named acting CEO and here, 8 years later, he continues to serve in that role.

* Results: Mentor stock in May 2008 was at about $11.50/share, by June 2008 it had moved to $16, by October 2008 it was down to less than $8, and by March 2009 was barely above $4. Ouch.

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Mark Gilbert: White coat, White hat, Big fish

Thursday, June 30th, 2016

 


Exuberance and Optimism:
the only two words required to describe EDA-Careers’ Mark Gilbert – even after 20 years in the trenches sorting out the who what and where of just about everybody in the EDA industry. Yes, he self-identifies as the fun guy in the white suit, seen hither and yon wherever the EDA Nation chooses to confab, but in reality he’s the good guy in the white hat who’s going to tell it to you straight, about your career and your goals.

Also by his own description, Mark Gilbert is “the big fish in a little pond” who serves as the leading head hunter and career counselor extraordinaire of EDA.

I was lucky enough to speak with Gilbert by phone this week. As he and I were both on the East Coast, coordinating the hour of the call was easy. Our conversation started with the usual query: How did you get started in this business?

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Verific: Rhymes with Terrific

Thursday, June 23rd, 2016

 


Michiel Ligthart
, President and COO of Verific Design Automation, and Rick Carlson, VP of Worldwide Sales, have a proposal for young companies in the EDA industry and adjacent technologies: Come to Verific if your organization is early stage, in need of encouragement and wise counsel, and could benefit from access to Verific software to help you progress towards a commercial product launch.

In a recent phone call, Ligthart and Carlson explained the specifics of the Verific program, and delineated what it’s not: “We are not funding startups,” Ligthart said, “but we have changed our business model over the lifetime of our company to encourage innovation.

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Accellera’s PSWG: Realists and Optimists, the lot of them

Thursday, March 17th, 2016

 


Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon
several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.

After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.

I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?

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Attending DVCon: Read this first …

Wednesday, February 24th, 2016

 


Emulation is everything in verification today
and therefore at the center of DVCon. Technology expert, Lauro Rizzatti, has prepared this brief tutorial for you, so you’ll be ready for the conference that starts on February 29th.

* The Past

Hardware emulation has been around for 3 decades. It started in the mid 80s with pioneers like Quickturn and Ikos, who used off-the-shelf FPGAs in the fabric of their emulators. The second decade saw the rise of several startups, some of them using custom silicon devices in the emulators.

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Hypothetical Stock Index: Lip-Bu Tan vs. EDAC

Wednesday, January 20th, 2016

 


Just short of 2 years ago
, the EDA press corps sat in a room in the Hyatt Regency in Santa Clara and enjoyed a face-to-face with Cadence CEO Lip-Bu Tan. A full report of that conversation is available here, but it is the closing segment of the report that informs this blog:

Finally, the Cadence PR machine closed out the hour by making sure the Press Corps was privy to the human side of CEO Tan. It would appear his wife does not make the tech-product purchasing decisions at home as much as do the two boys. Tan said that his two CMU-educated engineer sons are smart and savvy, and had advised him early on to invest in both Netflix and Tesla. Tan humbly acknowledged that he had, unfortunately, ignored those two pieces of advice and hence had lost out on the opportunity to win big in both movies and EVs.

So, here’s the hypothetical: Given Lip-Bu Tan’s involvement with a $2 billion investment group – efforts interleaved with his responsibilities as Cadence CEO – wouldn’t it have been wise to harvest stock tips from his press meeting back in March 2014 in Santa Clara?

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DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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