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Posts Tagged ‘Karen Bartleson’

Madam President: IEEE’s Bartleson brings honor to EDA Nation

Thursday, December 8th, 2016

 


For the first time ever, a citizen of the EDA Nation will be President of the IEEE
, with 400,000+ members, the largest professional organization in the world. Karen Bartleson is serving as IEEE President-Elect here in 2016, and will serve as IEEE President starting in January 2017.

Prior to her current role at IEEE, she was President for two years of the IEEE Standards Association, a group with total membership exceeding 17,000. And prior to her leadership there, as every citizen of the EDA Nation knows, Bartleson honed her myriad skills through 20 years of distinguished service at Synopsys.

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#52DAC Day Zero: Ten Astonishing Bits

Sunday, June 7th, 2015

 

Omygosh, DAC’s here again! Has it already been a year? Apparently yes, and apparently once again the Design Automation Conference is going to be great. And how does one know? Because once again the DAC Executive Committee is great, lead in 2015 by the more-than-capable Anne Cirkel (Mentor’s own). Everything from academia to industry, from networking to hard-core learning (read, ‘Nerd Alert!)’, from food and libation to product announcements: DAC is always special.

So today is Sunday, which in the world of DAC is a lovely day full of workshops for those interested in the newest, and social opportunities for those interested in the noshing and nattering. Sunday is also lovely, because it’s a moment for astonishing realizations, and this year’s 52nd DAC Sunday is no different. Here are my 10 favs:

10 — Per Stanford’s Philip Wong speaking in Workshop 2, carbon nanotubes are smooth which helps with mobility-restricting surface roughness and band-gap issues. Also CNTs are no longer “a bowl of spaghetti” when manufactured. Now they’re 99% orderly and courteously aligned. (read, ‘Is asking about the other 1% a legitimate question?’)

9 — EDA’s own Karen Bartleson of SNPS fame, has not only just completed 2 years of distinguished service as President of IEEE’s worldwide Standards Organization, she’s now been nominated to serve as President of the Whole Enchilada; Bartleson’s running for President of the IEEE itself. In a word, Wow!

8 — Design Automation Summer School, for those who have not been keeping up (read, ‘me’), is no longer a week-long confab in July. These days Summer School is a one-day event on DAC Sunday. Still highly attended and full of pithy content for The Young & The Restless in EDA.

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D&VCon: A labor of love for Krolikoski & Co.

Thursday, February 13th, 2014

 

If ever there was a year when you thought to attend DVCon, this should be it, according to a recent phone call with Cadence Fellow Stan Krolikoski, serving as General Chair for the second year in a row. That’s because DVCon 2014 will be serving up the D and the V in equal measure, and won’t be skewed towards the V in DVCon as it has been [perhaps] in the past.

Per Stan, “We’ve gotten feedback every year from attendees that they want more emphasis on design. They say they like verification, but they want more design, so last year I gave marching orders to the Technical Program Committee [headed by Paradigm Works’ Ambar Sarkar] that they should add more people on the review committee who represent design.

“It’s actually been a long time in coming. Although last year was the 25th anniversary of the conference, 10 years ago the name was changed to DVCon. Prior to that, it was HDLCon and the content reflected that name. When the name was changed to DVCon it was supposed to include both design and verification, but [functional verification emerged as the larger focus].”

That focus meant that those types of experts tended to dominate attendance, according to Stan, but that’s been fixed this year: “We will still have excellent functional verification sessions at DVCon – everything for the beginner through to the guru, it’s all there – but we will also have sessions on low-power design, on analog/mixed signal, and on system-level design, as well as IP integration. We’re clearly moving away from just verification in adding lots of design content to the program that’s of interest to our audience.”

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Aart de Geus: Smartest guy in the room

Wednesday, October 16th, 2013

 

Several years ago, after a phone briefing about a new product launch, I received a call back from the PR counsel who had organized the meeting. She asked me if I had all the info I needed regarding the product and the company. I said yes, and offered a minor apology for asking too many pointed questions of the marketing manager during the interview.

She said, “Oh, that’s okay. Talking to you is like talking to Aart de Geus. It’s clear you both think you’re the smartest guy in the room.”

That comment has come to mind multiple times since then, for two reasons. One, you never really know what impression you leave with people until it comes out at some capricious moment. And two, Aart de Geus isn’t the smartest guy in the room, just because he thinks so. He’s the smartest guy in the room, because he really is the smartest guy in the room.

That’s particularly applicable today with the EDAC event celebrating the 50th Anniversary of the EDA industry about to commence this evening in Silicon Valley. Per the Consortium, a plethora of industry luminaries will be in attendance. Per this writer, none will be more luminary than Dr. de Geus. If you’re reading this, you’re probably pretty well versed in both the history of EDA and the history of Aart de Geus. Nonetheless, here’s the latter in a nutshell.

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Pop Quiz: The Standards Game

Friday, February 17th, 2012

 

Here’s your February Pop Quiz.

******************

1 – DVCon 2012 starts on February 27th. The conference was first held in _____.

a) 1989
b) 1995
c) 1998
d) 2003

2 – The IEEE Standards Association [IEEE-SA] oversees approximately _____ standards and _____ standards under development.

a) 500, 900
b) 800, 600
c) 900, 500
d) 700, 900

3 – The IEEE Standard associated with VHDL is _____.

a) IEEE Std 1064
b) IEEE Std 1076
c) IEEE Std 1164
d) IEEE Std 1176

4 – Accellera merged with _____ in 2011.

a) VSIA
b) OSCI
c) OCP-IP
d) OVI

5 – DVCon is managed by MP Associates, the same group that manages _____.

a) ICCAD
b) DesignCon
c) Semicon
d) ISQED

6 – The 2007 General Chair of DVCon was _____.

a) Tom Fitzpatrick
b) Stephen Bailey
c) Shankar Hemmady
d) Gabe Moretti

7 – SystemVerilog was donated to Accellera in _____.

a) 2000
b) 2001
c) 2002
d) 2003

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DVCon: You will be Tested

Friday, February 10th, 2012

 

Pay close attention. You will be tested on the following.

DVCon stands for Design & Verification Conference. Not surprisingly, it’s targeted at design and verification engineers. Despite rumors on the street, design and verification engineers are still two different types of employees, particularly at the big design houses. That’s why DVCon is applicable to both. Two disciplines. One conference.

DVCon happens every year around this time at the Double Tree Inn in San Jose. Approximately 700 people attend. The conference is 4 days long, including 2 days of tutorials on either side of 2 days of technical sessions. There’s always one major panel, this year on February 28th, that showcases industry execs. Famously, it used to be moderated by John Cooley. Now it’s moderated by JL Gray, who is also famous.

JL’s panel this year will include Ted Vucurevich, John  Costello (sic erat scriptum), Gary Smith, and Jim Hogan. If you do not know who these people are, perhaps you should not be coming to DVCon. Unless you’re a design or verification engineer, in which case that’s okay. You’ll probably know someone on the panel the next day hosted by Brian Bailey, who is not famous. He is legendary. Brian’s panel is about Hardware-Assisted Verification and includes people from Qualcomm, ARM, SpringSoft, Xilinx, and Cadence.

DVCon also has a major keynote, this year on February 29th, which features the CEO of one of the Big 3 EDA companies. Last year it was Mentor’s Wally Rhines. This year it’s Synopsys’ Aart de Geus. His talk is entitled: Principles for Success in IC Design. DVCon is well known for this type of positive thinking. Last year, JL Gray’s panel was entitled: Making Great Products Great. This year it’s entitled: The Resurgence of Chip Design. You will not find a keynote at DVCon entitled: Principles for Failure in IC Design, nor a panel entitled: Making Great Products Lousy. That kind of thinking is not what DVCon is all about.

DVCon is sponsored these days by Accellera Systems Initiative, a single organization created last year out of two separate organizations, Accellera and OSCI. That’s because both organizations are interested in system-level design. NASCUG is also interested in system-level design. It too has a presence at DVCon. If you don’t know what NASCUG means, click here. Meanwhile, remember that Accellera was itself created in 2000 out of two separate organizations, OVI and VHDL International. This type of thing is also what DVCon is all about. People helping people make their organizations better. People helping people figure out how we can all get along.

Creating standards is another way of figuring out how we can all get along. Which brings us to Karen Bartleson. Like Accellera Systems Initiative, Bartleson is a single person who represents two complementary ideas: Standards and Positive Thinking. This is why Karen is the perfect person to be General Chair of DVCon. She is Synopsys’ go-to person for all things related to Standards, and she is nothing, if not all about Positive Thinking. Add these together, and multiply by two, and you see why this is the second year in a row that Karen has been DVCon General Chair.

Karen will not be General Chair next year. She will be busy doing something else. She will be serving as President of the IEEE Standards Association, overseeing 900 different standards and the 15,000 people who maintain and update those standards. Maybe she could invite all of those people to DVCon in 2013, although it might get a little crowded if they all came. MP Associates, the folks who run DVCon (and DAC among other things), might run out of conference bags. Nonetheless, MP Associates is a very capable organization. If Karen Bartleson got all 15,000 IEEE standards committee members to come to DVCon next year, I’m sure that MP Associates would be up to the task.

Speaking of people who like people, that brings us to the idea of networking, wine/beer, and exhibit halls. DVCon serves up a generous dollop of all three, along with the tutorials, keynotes, panels, and technical sessions. I have checked with Karen Bartleson and she assures me that when the DVCon 2012 Exhibit Hall is open – February 28th from 3:30 to 6:30 pm, and February 29th from 4:00 to 7:00 pm – there will be lots of networking, food, wine/beer, and sanctioned recruiting amidst the 30+ exhibitor booths.

She also emphasized that the wine/beer will be complementary to all attendees. That might be a tall order for next year if 15,000 people come to DVCon. All the more reason why you should be planning to come this year. Serving up wine and hors d’oeuvres to 700 people is an order of magnitude easier than serving same to 15,000. Even if highly capable MP Associates could pull it off. Or if DVCon organizers could afford it.

Speaking of money, DVCon is good there as well. They have made enough money to be profitable several years in a row. Accellera Systems Initiative, apparently, also has some extra money because they will be presenting a monetary award to the Best Paper winners at DVCon. Yet another reason to attend. The Best Paper selection will be done by the attendees themselves, voting throughout the conference to determine who will be announced Big Winner in the last session on February 29th. Karen said receiving Best Paper at DVCon is something special, particularly given the quality of the papers submitted.

Okay, if you’ve read carefully to this point, there’s only three things left to do.

* Register for DVCon.

* Watch Karen Bartleson’s upcoming Conversation Central interview with the DVCon 2012 Technical Program Chair and Tutorials & Panel Chair on February 16th.

* Take the quiz, which will be posted here on February 17th.

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CST: Webinar series
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