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Posts Tagged ‘Intel’

At the Verification Bar: Solutions from Here to Eternity

Thursday, September 26th, 2013


A Professor, a Sage, and a Guru walked into a bar. Brian the Bartender, greeted them: “What’ll it be, boys?”

The Professor said, “We need some help, Brian, settling an argument.”

“No problema,” Brian the Bartender said. “I’ve got an answer for everything.”

“Well,” the Professor said, “I think ESL’s not going to happen in our lifetime, but the Guru here says it’s just around the corner now that he and his have finally got all the pieces of the flow in place.”

Brian the Bartender laughed, “Yeah, the Guru’s been saying that since the dawn of mankind!”

“Exactly,” the Professor said.

Again Brian the Bartender laughed, “Guru, can you defend yourself? And don’t even think about plunking your wordy White Paper down on the bar. This is a public house, not a public library.”


Herb Reiter: The three-legged stool of Technology Choices

Thursday, September 5th, 2013


Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.


EDPS 2013: surf, sand, serenity, semiconductors

Thursday, April 4th, 2013


Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.

Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.


GSS: a spirited defense of FDSOI

Thursday, December 13th, 2012


When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.

Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.

We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”


M&A: Rumor dampens spirits over cocktails

Tuesday, October 2nd, 2012


It’s not often that the rumor hits the fan that Synopsys is buying EVE, it’s not often that you’re standing in a cocktail party at a tech conference in the South of France, and it’s not often that these two events happen simultaneously.

When the Synopsys/EVE rumor swept through the cocktail party in Sophia Antipolis on this first evening of the SAME Forum, not surprisingly a lot of people had opinions. This is not just a tech conference, after all, it’s a microelectronics conference with an emphasis on design; EDA is at the center of the conversation.

This is also Europe and at the moment EVE, headquartered in France, is the darling of the EDA ecosystem on the Continent. The company is doing very well, is felt to be holding its own in a series of lawsuits with Mentor Graphics, and is widely admired overall. Needless to say, the reaction over cocktails that EVE may go the way of SpringSoft and Magma was not one of jubilation. Just the opposite, in fact.


Valin strategy: Invest in employees & counter-cyclical industries

Wednesday, September 5th, 2012


There are thousands of companies based in Silicon Valley, but not all of them focus on the long-term play. Valin Corp. does have that focus, however, intentionally balancing their product portfolio across a range of industries, and investing in their employees with equal intensity.

Company President & CEO Joe Nettemeyer told me in a recent phone call that this strategy has allowed Valin to grow non-stop over the last half-decade: “We’ve achieved growth through a combination of internal development and acquisition, averaging 20-percent growth or more, per year, over the last 5 years, even in spite of a slight hiccup in 2009. We like to invest in industries that are counter-cyclical to each other. When there’s a slow-down in one area, we can cover the slack with revenue in another.

“We’re an infrastructure company working in the wafer-fab-equipment end of the semiconductor industry, designing and building system solutions for companies around the world that make semiconductor-based products. We just completed a project with AKT that makes equipment for large flat-screen panels to retrofit 30 systems for Samsung.

“We’ve also expanded our capabilities in other industries over the years, particularly as a strategic global distributor for Applied Materials. We’re recognized as one of the top 40 industrial distributors in the nation based on our sales revenue, and have just been recognized as one of INC Magazine’s 500/5000 fastest growing companies in America.


DAC 2012: Wicked Wednesday in San Francisco

Sunday, May 13th, 2012


DAC looms!

If you do nothing else on Wednesday, June 6th, at the Design Automation Conference be sure to attend the second of the two keynotes.

Intel’s Brad Heaney will be talking about “designing a 22nm Intel Architecture Multi-CPU and CPU.” It’s got well over a billion transistors and would have only been the stuff of Sci-Fi dreams a brief 15 or 20 years ago.

After that, just like on Terrible Tuesday, you’ve got a wicked wheelbarrow full of different ways you could go, starting with the User Track. The Wednesday line-up in this well-received recent addition to the DAC schedule includes:

* Packaging & Automatic P&R, with speakers from Mentor Graphics, Samsung, and Intel
* Keynoter Q&A, with the morning’s IBM & Intel speakers fielding questions from the crowd
* Practical Formal Methods, with speakers from IBM, Oski, and Intel

If your interests, however, reside with the young more than the mega-organizations in the EDA ecosystem, Wednesday is your day to visit the ACM Sigda University Booth in the Exhibition Hall, where the “new EDA tools, EDA tools applications, design projects, and instructional materials” will be your guide to the future minds of this industry.


SAME: Microelectronics in the South of France

Thursday, May 3rd, 2012


The Sophia Antipolis Microelectronics Forum takes place every fall in the ‘Silicon Valley’ of Southern France, Sophia Antipolis, 5 miles inland from the beautiful Mediterranean city of Antibes.

Sophia Antipolis is about 20 minutes from the International Airport at Nice, with offices for approximately 800 high-tech companies – included among them: ARM, Broadcom, Cadence, HP, IBM, Infineon, Intel, Mentor Graphics, Nvidia, STMicro, and Synopsys – housed in a range of buildings set among the rolling hills of the enclave. Within that forested place and 800 enterprises, almost 40,000 people are employeed. There are also two college campuses in Sophia Antipolis, as well as restaurants, a golf course, multiple hotels, and a tennis institute.

In other words, if you’ve never been to the Cote d’Azur, never been to Nice or Antibes, if you think you’d love vistas across the wide blue Mediterranean Sea, want to learn more about good food, wine, Picasso, Matisse, ancient Greeks, the French Riviera, or microelectronics – and not necessarily in that order – you’re going to be wanting to go to the Sophia Antipolis Microelectronics Forum taking place this year on October 2nd & 3rd.


Rajeev Madhavan: The Road Not Taken

Tuesday, April 24th, 2012


There’s good news and bad news, in my opinion, with regards to Rajeev Madhavan, founder and CEO of Magma Design Automation, a company that was acquired by Synopsys on February 22, 2012.

The good news it that Rajeev is available to the press for candid interviews like the one included below. The bad news is Rajeev is not going to be part of the EDA landscape as he explores various options for the next phase of his life – and that means the industry will be just that much less interesting, at least for a while.

We spoke by phone in late February.


Peggy: Hey, Rajeev, how are you doing?

Rajeev: I’m doing pretty much okay as I think about what’s next. I’ve got opportunities, and I’ve got other interests I can now pursue – most people rarely get this kind of opportunity in life, so I’m grateful.


OVPs: old ideas made new

Sunday, April 15th, 2012


Open Virtual Platforms are an idea whose time has arrived. That is, if you understand what they are. Certainly, if you’re reading this blog, you know what a virtual platform is.

“Platform virtual machines are software packages that emulate the whole physical computer machine, often giving multiple virtual machines on one physical platform.”

For additional clarity, check it out on Wikipedia, paying particular attention to the incredibly dense/complex table found there that attempts to catalog various virtual platforms, their origins, supporting organizations, and features.


Imperas & Open Virtual Platforms

So, if that’s what virtual platforms are, then what are Open Virtual Platforms, OVPs?

Imperas – an enterprise founded in Silicon Valley in 2008 – would like you to understand and use OVPs. To do that, they are sponsoring a portal-based community called Open Virtual Platforms – a resource  designed to help chip developers have access to various open source virtual platforms, or models, of various commonly used hardware platforms endemic to the embedded systems world.


S2C: FPGA Base prototyping- Download white paper

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