Posts Tagged ‘Intel’
Wednesday, October 26th, 2016
Last week on Friday and Saturday, the IEEE Council on EDA hosted a 2-day workshop to discuss the future of design automation. Mentor Graphics provided the venue – a large conference room in their Fremont/Silicon Valley campus – and workshop leaders, UCSD Prof. Andrew Kahng, UCSD Prof. Farinaz Koushanfa, and Intel alum/CEDA President Shishpal Rawat provided the welcome.
Over the two days, a group of 50+ attendees – representing a wide cross-section of academics and industry experts – launched into conversations that were lively, energized, at times contentious, and completely engrossing. Put simply, there was no better place on the face of the globe on October 21st and 22nd where tech junkies were more intellectually challenged and entertained than at the Design Automation Futures Workshop in Fremont.
What made the workshop so compelling? For this, their inaugural DAFW, CEDA chose to address neuromorphic computing – the ultimate hotness related to machine learning, with a lot of promise for future applications. It doesn’t get any more design futures, or futuristic, than this.
Thursday, March 17th, 2016
Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.
After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.
I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?
Thursday, November 5th, 2015
Since initiating their Decoding Formal Club in October 2013, Oski Technology has hosted this much-needed get-together every quarter, most recently on October 21st of this year at the Computer History Museum in Mountain View. I was fortunate to attend the debut meeting in 2013, so it was interesting to hear from Oski VP Jin Zhang that the support group is proving valuable to the growing numbers who attend.
“The first time we held the meeting,” Zhang said, “it was by invitation only, and we included about a dozen folks. Since that first event, we have continued to use the same room at the Computer History Museum, a room that can hold up to 40 people.
“The workshop, however, is continuing to grow very nicely, so we are faced with either finding a new venue or working with the museum to arrange for a bigger room for our next meeting in the first quarter of 2016.”
Zhang said interest in the event has increased to the point that people sign up to attend as soon as the date and time are announced. “They want to be sure they’ve got a spot,” she said.
Thursday, September 3rd, 2015
Alain Labat, the former President & CEO of VaST Systems, told me on a phone call this week that his story, in a way, is very simple: “When we got acquired by Synopsys in 2010, 5 years ago now, our management and investors clearly saw an opportunity to start our own investment bank and advisory company, so that’s what we did.
“We believed then, and still believe, that if you need a big bank from New York or a huge amount of money [to begin your enterprise], the right people are the Goldman Sachs or the other Wall Street guys. But for a technology-based company, you need something different.
“And so, at the advice of our investors, we started Harvest Management Partners specifically for those companies who need something different. Coming from VaST as we did, with a great deal of true operational experience, we felt we could offer much-needed guidance to those companies who were not a good fit for Wall Street.
Sunday, June 7th, 2015
Omygosh, DAC’s here again! Has it already been a year? Apparently yes, and apparently once again the Design Automation Conference is going to be great. And how does one know? Because once again the DAC Executive Committee is great, lead in 2015 by the more-than-capable Anne Cirkel (Mentor’s own). Everything from academia to industry, from networking to hard-core learning (read, ‘Nerd Alert!)’, from food and libation to product announcements: DAC is always special.
So today is Sunday, which in the world of DAC is a lovely day full of workshops for those interested in the newest, and social opportunities for those interested in the noshing and nattering. Sunday is also lovely, because it’s a moment for astonishing realizations, and this year’s 52nd DAC Sunday is no different. Here are my 10 favs:
10 – Per Stanford’s Philip Wong speaking in Workshop 2, carbon nanotubes are smooth which helps with mobility-restricting surface roughness and band-gap issues. Also CNTs are no longer “a bowl of spaghetti” when manufactured. Now they’re 99% orderly and courteously aligned. (read, ‘Is asking about the other 1% a legitimate question?’)
9 – EDA’s own Karen Bartleson of SNPS fame, has not only just completed 2 years of distinguished service as President of IEEE’s worldwide Standards Organization, she’s now been nominated to serve as President of the Whole Enchilada; Bartleson’s running for President of the IEEE itself. In a word, Wow!
8 – Design Automation Summer School, for those who have not been keeping up (read, ‘me’), is no longer a week-long confab in July. These days Summer School is a one-day event on DAC Sunday. Still highly attended and full of pithy content for The Young & The Restless in EDA.
Wednesday, April 22nd, 2015
If there’s something missing in your personal or professional knowledge of Moore’s Law, you should have spent 5 hours at the Computer History Museum in Mountain View on April 17, 2015, although even then you might not have learned anything new. For people in technology, seriously, what more is there to know?
The ‘law’, penned by Gordon Moore and published in an Electronics article on April 19, 1965, was based on his many years’ experience in the nascent-to-ferocious semiconductor industry, and has since been interpreted, re-interpreted, mis-interpreted, and zealously lionized – both the law and the man – over the last 50 years. Which brings us back to April 17th and the 3-part program at the CHM.
Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run
wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
Thursday, October 16th, 2014
There are three types of Italian genius. Leonardo da Vinci characterized one with his brilliant problem solving, creative innovations in the arts and sciences, diverse dabblings that often left completion dates for commissioned projects as sfumato as his oils, and aggressive self-promotion. An apocryphal testimonial to this last: When he finished the Mona Lisa in the early 1500s, he invited friends and foe alike into his studio to show off what he assured them would be the Next Big Thing. Humility was not in Leonardo’s toolkit.
Born in 1475, Michelangelo Buonarroti exemplified a second type of Italian genius. Intense, focused, gifted with extraordinary talents in the visual arts and architecture, and rumored to be so impassioned by his work as to go weeks on end without sleep, his talent was such that monumental commissions were forced upon him by the political and religious powers of the day, although he argued bitterly against the scale of such assignments. He became increasingly cantankerous with age, and in angry response to criticism of one commission in particular, famously painted himself into his vast Last Judgment as a flayed skin victimized by his patrons. Charm and affability were not in Michelangelo’s toolkit.
Fast forward five centuries and find now a completely different type of Italian genius. Shaped by mid-20th century forces in technology, and brought to full fruition in the fertile fields of Silicon Valley, Lucio Lanza exemplifies a third class in the taxonomy, one that encompasses the upsides of those 16th century icons – intelligence, creativity, a passion for innovation and work, a sense of history – without the downsides – egomania, rough irritability, inability to finish a project, or avoid a project too big to handle.
In the wake of two High-Renaissance Florentians, it took one High-Tech Milanese to fill out the taxonomy of Italian genius. Here in the 21st century, Lucio Lanza is in a modern class of his own.
Thursday, September 25th, 2014
Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat, and when I say chance that’s accurate. Rawat is so busy these days, it’s hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.
Among other activities, both Accellera and CEDA sponsor several key conferences in the industry. Accellera is the primary sponsor of the Design and Verification Conference and Exhibition (DVCon). I asked Shishpal about this year’s efforts to take DVCon on the road and how that dovetails with the changes he’s seen at Accellera over his years of leadership.
He said, “Without a doubt, the biggest change is the international outreach that we are now doing in our programs. DVCon will debut in Bangalore this month and will debut in Europe next month on October 14th and 15th in Munich. Expanding the conference this way has required a great deal of work on the part of local dedicated volunteers in both India and Europe, in addition to the efforts of our established corps of hardworking people. We expect a very big group of attendees at both of these shows, which adds to the work load for everyone involved.”
Tuesday, June 10th, 2014
UMass Amherst’s Sandip Kundu moderated a Thursday afternoon panel at DAC entitled, ‘Designing on Advanced Process Nodes: How many re-spins should you plan for?’
In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.
Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”
It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.
Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.