Posts Tagged ‘IBM’
Thursday, March 17th, 2016
Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.
After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.
I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?
Monday, February 16th, 2015
Lauro Rizzatti, formerly VP of Marketing at verification-centric EVE, thought he was going to move to Oregon last year and retire, but he was wrong. Instead he is busier than ever, hard at work both in the EDA tech sector and in the larger world of venture capital.
Lauro is consulting with Mentor Graphics to promote the company’s ever-expanding presence in the world of emulation, and he is also involved with the Oregon Angel Fund, a group of investors led by Eric Rosenfeld and former SpringSoft USA President Scott Sandler, also busy residents of Oregon.
Mentor is one of the top two emulation companies in the world, along with Cadence. Synopsys also has a foot in the door of that market thanks to their 2012 acquisition of EVE, which brings us back to Lauro. It was after his year spent at Synopsys following the acquisition that he ‘retired’ to Oregon. Clearly, however, it was a waste of his 30+ years of experience in verification to not have him continue contributing to the conversation around that technology, hence his consulting work at Mentor.
I had a chance to talk with Lauro about all of this in a recent phone call, a discussion in which he celebrated the green of Oregon while also gently chiding the endless rain that makes that lushness possible.
Thursday, November 13th, 2014
Dreary sentiments notwithstanding from several panelists at an ICCAD evening session on November 2nd in San Jose, SRC’s Dr. Bill Joyner espoused optimism and energy for the future of EDA, even if said future doesn’t include the venerated Moore’s Law stretching off into infinity forever.
As moderator, Joyner convened the panel, “Moore’s Law is dying, EDA to the rescue!”, and turned over the podium straightaway to University of Pittsburgh’s Dr. Alex Jones for the first 20 minutes, which allowed the professor to report out on a 3-year Computing Community Consortium effort, just completed, to examine and exhume EDA from the doldrums.
The CCC’s group of 50+ academic and industry leaders have been meeting since 2012 at a series of SIGDA/CCC-funded workshops hoping to impact the future by nudging industry and academia into more productive avenues of research and development in design automation.
The report the committee published, “Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond”, was available in paper form at the back of the room during the ICCAD panel and has subsequently proved to be great reading, and fodder for a future blog. But this blog is a thumbnail sketch of the November 2nd discussion, so please read on.
Thursday, April 24th, 2014
Talking to ProPlus Design Solutions requires a long view of history over at least the last 20 years in EDA. In 1993, BTA, an EDA company focused on device model extraction and SPICE simulation, was founded with U.C. Berkeley’s Dr. Chenming Hu as Chairman of the Board. In 1999, BTA merged with Ultima, and became Celestry in 2001.
Finally, in 2003, the combined companies were acquired by Cadence Design Systems. Then in 2007, a new company called ProPlus was spun out of Cadence to support the original BSIMProPlus device modeling platform with roots going back to BTA/Celestry.
Current ProPlus CTO Bruce McGaughy earned his PhD at Cal with Chenming Hu as his advisor, served at both BTA and Celestry, and worked at Cadence, before joining ProPlus 6 years ago. I had a chance to talk with Dr. McGaughy in person last month in Silicon Valley. Our conversation covered a range of topics.
Thursday, September 5th, 2013
Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.
In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.
Fully-depleted SOI …
Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.
“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.
Thursday, June 13th, 2013
Every year, Forbes publishes a list of the Best Companies To Work For. The winners are always big companies, ones well known by you and me. The problem is that Forbes’ polling techniques are flawed. If they were not, EDA stalwart Real Intent would most definitely make the list, particularly if the folks from Forbes were to have been in on a recent phone call with Real Intent President & CEO Prakash Narain.
Tuesday, June 4th, 2013
The only thing most people remember about Tuesdays at DAC are the parties. You’re a success if you attended at least two, less than a success if you only attended one, and guaranteed immortality if you attended more than three.
Of course, other things happen on Tuesdays at DAC – early morning breakfasts where sincere technologists present and/or opine about somber challenges facing the industry, the plenary session, presentation of multiple awards, pavilion panels, mid-day luncheons, afternoon sessions, posters, and many, many hours logged in by booth staff talking and talking and talking to customers, potential customers, and general industry hangers-on looking for free give-aways.
Wednesday, May 15th, 2013
Not all of the 1600+ people who attended DATE 2013 earlier this year in Grenoble were able to fit into the room where the panel celebrating 30+ years of the Mead-Conway VLSI Revolution took place. Those who could, however, were treated to a lively 90 minutes of conversation on what that revolution meant to the world of electronics and chip design.
Organized by Synopsys’ Marco Casale-Rossi and moderated by U.C. Berkeley’s Alberto Sangiovanni-Vincentelli, panelists included Berkeley’s Jan Rabaey, IMEC’s Hugo de Man, CMP’s Bernard Courtois, Columbia University’s Luca Carloni, and Synopsys’ Antun Domic.
Although I was among those disappointed to have missed the event, I was able to speak after the fact with Antun Domic. He described the ambiance of the SRO session in Grenoble and enumerated several of the points laid out by the panelists, starting with their praise of Lynn Conway and Carver Mead’s ground breaking text book, published in 1980, Introduction to VLSI Systems.
Thursday, March 7th, 2013
IBM’s Brad Brech gave one of the Tuesday morning keynotes at ISQED 2013 on March 5th. It was a thought-provoking talk and well received by a large audience of engineers at the Techmart in Santa Clara. Per Brech, like everywhere in computing the trend in data centers is “smaller, cheaper, and faster.”
To illustrate, he drew comparisons with developments in aeronautics over the last century, invoking the Wright Brothers’ aircraft, the Curtiss Flying Boat, the Boeing Stratoliner, the De Havilland Comet, the Boeing 707, and the Concorde. All of these aircraft, he said, addressed technology concerns related to speed. As tragically illustrated by the Concorde disaster in 2000, however, eventually speed as a lone metric of progress in commercial aviation proved unsustainable. Instead, after 2000 the industry became more concerned about efficiency and less about speed.
Similarly, Brech argued, now for the first time in the history of computing, “While CEOs are identifying technology as the single most important external force impacting their organizations, they’re not interested in the speed of the technology but how quickly and efficiently it can be brought online. Now the IT cycle is about speed to adoption and efficiency, not just about the latest/greatest software or hardware.”
Thursday, November 1st, 2012
The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.
In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.
Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.
“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.
“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”