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Posts Tagged ‘Herb Reiter’

Herb Reiter at EDPS: Multi-Die IC Design and Application

Thursday, March 24th, 2016

 


To speak with Herb Reiter about the rationale for multi-die packaging
is a chance to follow a logical and energetic continuum from first principles to a final conclusion. Namely, that as the era of the ASIC subsides, the era of the multi-die package will arrive full force.

Reiter, President of eda 2 asic, will be reiterating this line of thinking, in conjunction with a panel of like-minded experts, at the upcoming EDPS conference in Monterey on April 21st. In anticipation of that session – “Multi-Die IC Design and Application” – we spoke by phone this week. The conversation was compelling.

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EDPS: Conversation overlooking the sea

Thursday, April 3rd, 2014

 

There are lots of clever ways to tell you why it’s worth your while to attend EDPS in Monterey on April 17th and 18th. It’s less noisy than DAC, less vendor-specific than CDNLive, SNUG or U2U; less crowded than ISSCC; has fewer presentations than DVCon; and boasts no co-located events to confuse your schedule like at ISQED. But that doesn’t tell you why EDPS is worthwhile. It’s the list of speakers and the setting that should convince you to carve out some time on that Thursday and Friday to run down to Monterey – a scenic hour’s drive from Silicon Valley – to attend the 21st annual Electronic Design Process Symposium.

On Thursday, Wally Rhines is giving the keynote after dinner; during the day, Gary Smith’s moderating a session on design flow challenges that includes Frank Schirrmeister, John Swan, Gene Matter, Jim Kenney, and Naresh Sehgal; Sehgal’s leading a session on pre-silicon software development platforms that includes Camille Kokozaki, Shantanu Ganguly, Kumaraswamy Namburu, Schirrmeister, and Vicki Mitchell; Herb Reiter’s moderating a session on FinFETs, 3D-ICs, and FDSOI, that includes Jamil Kawa and Paul McLellan; and the kick-off keynote on Thursday morning will be given by Intel’s Chris Lawless talking about pre-silicon platforms for software development.

On Friday, Dan Nenni’s leading a whole day on IP that includes Martin Lund, Patrick Soheili, Warren Savage, Kurt Shuler, Lluis Paris, Carey Robertson, and Bernard Murphy. Finally, Aparna Dey is General Chair for EDPS. All together, that’s 24 people and a robust ecosystem of knowledge and experience comprising this year’s EDPS program.

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Herb Reiter: The three-legged stool of Technology Choices

Thursday, September 5th, 2013

 

Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

****************
Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.

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EDPS 2013: surf, sand, serenity, semiconductors

Thursday, April 4th, 2013

 

Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.

Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.

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EDPS: 3D-IC Showers & Flowers

Friday, April 6th, 2012

 

It’s April 2012, and both spring and 3D-ICs are in the air. But if Spring means April showers and May flowers, what do 3D-ICs mean?

Well, if you were at EDPS in Seaside this morning, at the Monterey Beach Resort, you would have heard from a host of speakers all addressing the April showers and May flowers of 3D-ICs. The session was organized and well moderated by eda2asic’s Herb Reiter.

* Showers –

Heat … 3D-ICs kick up a lot of thermal issues between the layers.

* Flowers –

Multiple solutions are under consideration for heat. If you’re rich like IBM, you talk about micro-channels where cooling waters will flow. If you’re not rich – like everybody else – you don’t yet know what to do to sink that heat off-chip and out of harm’s way. Micro channels are too exotic, so stay tuned as solutions are sought out and implemented.

* Showers –

EDA Flow … it’s not quite here, according to many, even though the current tools may be good enough for some. Most believe there are larger needs that should be met.

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Monterey: Top Ten @ EDPS

Thursday, March 29th, 2012

 

Here are the Top Ten reasons to be going to EDPS next week in Monterey:

10) Next week’s a lighter work week for most and the Monterey Peninsula is beautiful at any time of the year, but particularly in the spring.

9) The Electronic Design Process Symposium is in its 19th year, and everybody who’s anybody in EDA and its adjacencies has attended at one point or another.

Eight) The topics discussed at EDPS have always tracked the trajectory of the industry. In 2000, those topics included: deep sub-micron, distributed and web-based design methodologies, designer productivity, and maintaining modularity in an integrated design flow.

Here in 2012, technology evolution has driven a completely different set of topics: embedded processors, FPGAs, ESL, NUMA, EDA in the Cloud, Big Data and the Big Servers that serve them, low-power design, and 3d-ICs, among others.

7) Going to conferences is as much about conversations outside the sessions, as it is about presenting or listening within the sessions. EDPS is a boutique conference, where I promise you’ll have a chance for substantive conversations with the speakers, both inside and outside of the sessions.

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