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Posts Tagged ‘Grant Martin’

Martin, Lavagno, Scheffer, Markov: Assembling a Mighty Tome for the Ages

Thursday, July 13th, 2017

 


It was a great pleasure to sit down recently with Grant Martin
– Distinguished Engineer in the Tensilica R&D/IP Group at Cadence – to discuss the 2nd edition of the 2-book compendium he is so closely associated with:

Volume 1: Electronic Design Automation for IC System Design, Verification, and Testing
Volume 2: Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology

Grant Martin did not assemble and edit these mighty tomes as a sole practitioner. Also listed on the covers are Luciano Lavagno, Louis Scheffer, and Igor Markov – representing, respectively, the Politecnico di Torino, Howard Hughes Medical Institute, and University of Michigan.

All four of these remarkably accomplished technologists had a hand in the newest edition, although according to Grant Martin, it was he, Lavagno, and Scheffer who oversaw the original effort in 2006.

When the publisher suggested an update to the set in 2011 – 5 years on – it ended up taking so much longer, it was actually 10 years before the 2nd edition was complete. Meanwhile, Prof. Markov had joined in on the work in 2014, so was appropriately added to the list of editors in 2016.

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Monterey: Top Ten @ EDPS

Thursday, March 29th, 2012

 

Here are the Top Ten reasons to be going to EDPS next week in Monterey:

10) Next week’s a lighter work week for most and the Monterey Peninsula is beautiful at any time of the year, but particularly in the spring.

9) The Electronic Design Process Symposium is in its 19th year, and everybody who’s anybody in EDA and its adjacencies has attended at one point or another.

Eight) The topics discussed at EDPS have always tracked the trajectory of the industry. In 2000, those topics included: deep sub-micron, distributed and web-based design methodologies, designer productivity, and maintaining modularity in an integrated design flow.

Here in 2012, technology evolution has driven a completely different set of topics: embedded processors, FPGAs, ESL, NUMA, EDA in the Cloud, Big Data and the Big Servers that serve them, low-power design, and 3d-ICs, among others.

7) Going to conferences is as much about conversations outside the sessions, as it is about presenting or listening within the sessions. EDPS is a boutique conference, where I promise you’ll have a chance for substantive conversations with the speakers, both inside and outside of the sessions.

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Pop Quiz: The Standards Game

Friday, February 17th, 2012

 

Here’s your February Pop Quiz.

******************

1 – DVCon 2012 starts on February 27th. The conference was first held in _____.

a) 1989
b) 1995
c) 1998
d) 2003

2 – The IEEE Standards Association [IEEE-SA] oversees approximately _____ standards and _____ standards under development.

a) 500, 900
b) 800, 600
c) 900, 500
d) 700, 900

3 – The IEEE Standard associated with VHDL is _____.

a) IEEE Std 1064
b) IEEE Std 1076
c) IEEE Std 1164
d) IEEE Std 1176

4 – Accellera merged with _____ in 2011.

a) VSIA
b) OSCI
c) OCP-IP
d) OVI

5 – DVCon is managed by MP Associates, the same group that manages _____.

a) ICCAD
b) DesignCon
c) Semicon
d) ISQED

6 – The 2007 General Chair of DVCon was _____.

a) Tom Fitzpatrick
b) Stephen Bailey
c) Shankar Hemmady
d) Gabe Moretti

7 – SystemVerilog was donated to Accellera in _____.

a) 2000
b) 2001
c) 2002
d) 2003

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