Posts Tagged ‘GlobalFoundries’
Thursday, March 23rd, 2017
Something historic and poignant is taking place on Thursday, April 6th, that should be of interest to absolutely everyone in the EDA and IP communities. The four most powerful men in these two industries will be on stage for an ESD Alliance panel discussion led by Semiconductor Engineering’s Ed Sperling.
The four panelists include Synopsys Chairman & CEO Aart de Geus, Cadence President & CEO Lip-Bu Tan, Mentor Graphics Chairman & CEO Wally Rhines, and ARM CEO Simon Segars.
The April 6th event will be historic because these Big Four unequivocally define EDA and IP – just as Stanford, Huntington, Hopkins, and Crocker defined Railroads in the West – and it’ll be poignant because you’ll never see them together again. Too many changes ahead.
Of course, the ESDA panel will also be whimsical: You’ll know no more about these CEOs and their companies at the end of the evening than you knew when you first arrived. That doesn’t mean the evening won’t be entertaining.
Thursday, June 11th, 2015
It’s always hard to capture the spirit of any particular trade show/tech conference when it’s as large as DAC. So here’s just a small sample of the rumors and realities being bandied about at Moscone Center this week in San Francisco.
* Rumor: The Exhibit Hall ran until 7 pm on Wednesday night, so if you wanted to see the bagpipes close out the show, you could see it if you arrived at the Cadence booth by 6:45 pm.
* Reality: The Exhibit Hall closed at 6 pm on Wednesday, not 7 pm as on Monday and Tuesday. The bagpipes closed out the show, but at 6 pm, not 7 pm. Those who missed it were very, very sad.
* Rumor: DAC’s Exhibition Hall has shrunk so much over the last few years, it’s no longer going to be housed at Moscone Center. After next year’s DAC 2016 in Austin, the show’s headed to the San Jose Convention Center in 2017.
* Reality: Moscone Center is being renovated over the next several years, so DAC’s going to be in Austin in 2016, in Austin in 2017, and (probably) back in San Francisco in 2018.
Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run
wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
Thursday, November 13th, 2014
Dreary sentiments notwithstanding from several panelists at an ICCAD evening session on November 2nd in San Jose, SRC’s Dr. Bill Joyner espoused optimism and energy for the future of EDA, even if said future doesn’t include the venerated Moore’s Law stretching off into infinity forever.
As moderator, Joyner convened the panel, “Moore’s Law is dying, EDA to the rescue!”, and turned over the podium straightaway to University of Pittsburgh’s Dr. Alex Jones for the first 20 minutes, which allowed the professor to report out on a 3-year Computing Community Consortium effort, just completed, to examine and exhume EDA from the doldrums.
The CCC’s group of 50+ academic and industry leaders have been meeting since 2012 at a series of SIGDA/CCC-funded workshops hoping to impact the future by nudging industry and academia into more productive avenues of research and development in design automation.
The report the committee published, “Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond”, was available in paper form at the back of the room during the ICCAD panel and has subsequently proved to be great reading, and fodder for a future blog. But this blog is a thumbnail sketch of the November 2nd discussion, so please read on.
Wednesday, July 16th, 2014
Despite its ethereal-sounding name, Silicon Cloud International is a company grounded in the reality of chip design, particularly for an important international demographic, professors and students. Mojy Chian is CEO of the Singapore-based SCI. We spoke recently by phone.
Chian started by defining the cloud. “The concept of the cloud is straightforward. It means remote computing, so if you are not using your local machine, you are using the cloud. There are a lot of applications in the cloud, including eCommerce, Facebook, cloud storage, and remote collaboration based in the cloud.
“Certainly, usage of the cloud has taken off in recent years, but remember there are several different types of clouds. In contrast to private cloud computing, public cloud computing means accessing machines [owned by other companies such as Amazon], where you can actually go and use their machines.”
Our conversation being specific to chip design, I asked Chian to comment on widespread industry concerns regarding security when working in the public cloud. Companies are oft-times reluctant to compute and/or store their designs in the public cloud for fear of losing their precious data to hackers and pirates.
Tuesday, June 10th, 2014
UMass Amherst’s Sandip Kundu moderated a Thursday afternoon panel at DAC entitled, ‘Designing on Advanced Process Nodes: How many re-spins should you plan for?’
In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.
Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”
It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.
Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.
Thursday, July 25th, 2013
Ed Sperling, Editorial Director for Semiconductor Manufacturing and Design Community, moderated a breakfast panel on Tuesday morning, June 4th, at DAC. Having missed the bulk of the event, I was fortunate to have a chance later to review the slides of the five speakers: Cavium Networks VP Anil Jain, GlobalFoundries VP Subramani Kengeri and Director Kelvin Low, and Synopsys VP Raymond Leung and Senior Director Bari Biswas.
Having now gone through the slide deck twice, I’ve come away with a set of conflicting messages. On the one hand, the challenges of FinFET implementation are so great there is still much to be done, and the promise of the technology is yet to be fully proven. On the other hand, the synergy between GlobalFoundries and Synopsys is so excellent the challenges associated with FinFET implementation are definitely being met. So which is the more accurate message?
Thursday, July 4th, 2013
A note: Since composing this blog, the terrible crash took place at SFO. This tragedy is being felt keenly in the tech industry as it is possible that some of those on board were coming to San Francisco for Semicon West. Many people at the conference may have a special connection to the injured and/or have had their travel plans radically altered while SFO is attempting to deal with the aftermath. The people at EDACafe wish to express their deep concern for everyone affected by the accident.
This is clearly a holiday week, so most people are paying more attention to the barbeque than next week’s massive Semicon West in Moscone Center, so let’s keep this pre-event note short and to the point.
It is always [somewhat] telling to see who is and who is not sponsoring conferences, and Semicon West is no exception. What can be discerned, for instance, from the fact that GlobalFoundries is a sponsor of the conference this year, but TSMC is not? That Mentor Graphics and Synopsys both have their names on the sponsor list, but Cadence does not?
Tuesday, June 4th, 2013
The only thing most people remember about Tuesdays at DAC are the parties. You’re a success if you attended at least two, less than a success if you only attended one, and guaranteed immortality if you attended more than three.
Of course, other things happen on Tuesdays at DAC – early morning breakfasts where sincere technologists present and/or opine about somber challenges facing the industry, the plenary session, presentation of multiple awards, pavilion panels, mid-day luncheons, afternoon sessions, posters, and many, many hours logged in by booth staff talking and talking and talking to customers, potential customers, and general industry hangers-on looking for free give-aways.
Thursday, May 30th, 2013
In the old days, TSMC made a big toolflow announcement every year at DAC, and hosted a lively ‘partner pavilion’ where dozens of companies were showcased in small auxiliary booths that stood in addition to their conventional booths elsewhere in the Exhibit Hall.
At DAC 2103 in Austin, however, something different is happening. Hosted by GlobalFoundries, this year’s ‘foundry pavilion’ will showcase countries, not corporations: “The DAC Global Forum celebrates contributions and future plans of nations around the globe to the field of electronic design in past (sic) 50 years.” Should be very interesting; check out Booth #137 in Austin.
In the meanwhile, TSMC’s taking this week prior to DAC 2013 to announce various tool certifications, including FinFET v0.1 design enablement: “The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology.”
It’s always fun to read through these types of joint announcements, at least if you’re easily amused by the exercise of comparing the quotes embedded in dueling Press Releases. TSMC Senior Director Suk Lee, for instance, is quoted in all four press releases paraphrased below, sent out this week from ATopTech, Cadence, Mentor, and Synopsys.